LTC1735CS-1 datasheet(25/28 Pages) LINER

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LTC1735-1

APPLICATIO S I FOR ATIO

LTC1735-1. The VOSENSE line should not be routed

close to any other nodes with high slew rates.

3. Are the SENSE + and SENSE – leads routed together with

minimum PC trace spacing? The filter capacitor be-

tween SENSE + and SENSE – should be as close as

possible to the LTC1735-1. Ensure accurate current

sensing with kelvin connections to the SENSE resistors

shown in Figure 13. Series resistance can be added to

the SENSE lines to increase noise rejection.

4. Does the (+) terminal of CIN connect to the drain of the

topside MOSFET(s) as closely as possible? This capaci-

tor provides the AC current to the MOSFET(s).

5. Is the INTVCC decoupling capacitor connected closely

betweenINTVCC and the power ground pin? This capaci-

tor carries the MOSFET driver peak currents. An addi-

tional 1

µFceramicplacedimmediatelynexttotheINTVCC

and PGND pins can help improve noise performance.

6. Keep the switching node (SW), Top Gate node (TG), and

Boost node (BOOST) away from sensitive small-signal

nodes, especially from the voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and therefore should be kept on the

“output side” (Pins 9 to 16) of the LTC1735-1 and

occupy minimum PC trace area.

Figure 13. Kelvin Sensing RSENSE

Figure 12. LTC1735-1 Layout Diagram

COUT

RSENSE

4.7

µF

CIN

–

VIN

–

VOUT

1735-1 F12

COSC

RUN/SS

ITH

PGOOD

SENSE –

SENSE +

VOSENSE

SGND

BOOST

VIN

INTVCC

PGND

EXTVCC

LTC1735-1

47pF

1000pF

COSC

CSS

INTVCC

CC2

SENSE + SENSE –

HIGH CURRENT PATH

1735-1 F13

CURRENT SENSE

RESISTOR

(RSENSE)

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