DEVICES INCORPORATED

Video Imaging Products

13

LF3310

Horizontal / Vertical Digital Image Filter

11/08/2001-LDS.3310-H

COEFFICIENT SET 1

CLK

HLD/VLD

W1

W1: Coefficient Set 1 written to coefficient banks during this clock cycle.

HPAUSE/VPAUSE

CONFIGURATION REGISTER

CLK

W2

W1: Configuration Register loaded with new data on this rising clock edge.

HPAUSE/VPAUSE

SELECT REGISTER

W1

W2: Select Register loaded with new data on this rising clock edge.

HLD/VLD

HLD goes LOW, the Horizontal LF

The first value fed into the interface

determines what the interface is going

to load. The three most significant

or Configuration/Control Registers

(see Table 8). The nine least signifi-

whatever is to be loaded (see

Tables 9-14). For example, to load

address 15 of the horizontal coefficient

banks, the first data value into the

load horizontal limit register 10, the

first data value should be C0AH. The

first address value should be loaded into

the interface on the same clock cycle that

latches the HIGH to LOW transition of

HLD (see Figures 12 and 13).

The next value(s) loaded into the

interface are the data value(s) which

will be stored in the bank or register

defined by the address value. When

loading coefficient banks, the inter-

face will expect eight values to be

loaded into the device after the

address value. The eight values are

coefficients 0 through 7. When

loading select or Configuration

Registers, the interface will expect one

value after the address value. When

loading round registers, the interface

will expect four values after the

address value. When loading limit

registers, the interface will expect two

values after the address value.

Figures 12 and 13 show the data

loading sequences for the coefficient

banks and Configuration/Control

Registers.

Both HPAUSE and VPAUSE allow the

user to effectively slow the rate of data

When HPAUSE is HIGH, the LF

the Horizontal Filter is held until

HPAUSE is returned to a LOW.

When VPAUSE is HIGH, the LF

the Vertical Filter is held until

VPAUSE is returned to a LOW.

Figures 14 through 17 display the

effects of both HPAUSE and VPAUSE

while loading coefficient and control

data.

Table 15 shows an example of loading

data into the coefficient banks. The

following data values are written into

address 10 of coefficient banks 0

through 7: 210H, 543H, C76H, 9E3H,

701H, 832H, F20H, 143H. Table 16