LTC2223_15 datasheet(21/28 Pages) LINER

21 / 28 page

LTC2222/LTC2223

22223fb

APPLICATIONS INFORMATION

Figure 11. Transformer Driven ENC+/ENC–

In applications where jitter is critical (high input frequen-

cies) take the following into consideration:

1. Differential drive should be used.

2. Use as large an amplitude as possible; if transformer

coupled use a higher turns ratio to increase the

amplitude.

3. If the ADC is clocked with a sinusoidal signal, ﬁlter the

encode signal to reduce wideband noise.

4. Balance the capacitance and series resistance at both

encode inputs so that any coupled noise will appear at

both inputs as common mode noise. The encode inputs

have a common mode range of 1.1V to 2.5V. Each input

may be driven from ground to VDD for single-ended

drive.

Maximum and Minimum Encode Rates

The maximum encode rate for the LTC2222/LTC2223 is

105Msps (LTC2222) and 80Msps (LTC2223). For the

ADC to operate properly, the encode signal should have a

50% (±5%) duty cycle. Each half cycle must have at least

4.5ns (LTC2222) or 5.9ns (LTC2223) for the ADC internal

circuitry to have enough settling time for proper operation.

Achieving a precise 50% duty cycle is easy with differential

sinusoidal drive using a transformer or using symmetric

differential logic such as PECL or LVDS.

An optional clock duty cycle stabilizer circuit can be used

if the input clock has a non 50% duty cycle. This circuit

uses the rising edge of the ENC+ pin to sample the analog

input. The falling edge of ENC+ is ignored and the internal

falling edge is generated by a phase-locked loop. The input

clock duty cycle can vary from 20% to 80% and the clock

duty cycle stabilizer will maintain a constant 50% internal

duty cycle. If the clock is turned off for a long period of

time, the duty cycle stabilizer circuit will require a hundred

clock cycles for the PLL to lock onto the input clock. To

use the clock duty cycle stabilizer, the MODE pin should be

connected to 1/3VDD or 2/3VDD using external resistors.

Input Range

The input range can be set based on the application.

The 2V input range will provide the best signal-to-noise

performance while maintaining excellent SFDR. The 1V

input range will have better SFDR performance, but the

SNR will degrade by 5dB. See the Typical Performance

Characteristics section.

Driving the Encode Inputs

The noise performance of the LTC2222/LTC2223 can

depend on the encode signal quality as much as on the

analog input. The ENC+/ENC– inputs are intended to be

driven differentially, primarily for noise immunity from

common mode noise sources. Each input is biased

through a 6k resistor to a 1.6V bias. The bias resistors

set the DC operating point for transformer coupled drive

circuits and can set the logic threshold for single-ended

drive circuits.

Any noise present on the encode signal will result in ad-

ditional aperture jitter that will be RMS summed with the

inherent ADC aperture jitter.

VDD

LTC2222/LTC2223

22223 F11

VDD

ENC–

ENC+

1.6V BIAS

1:4

0.1μF

CLOCK

INPUT

50Ω

TO INTERNAL

ADC CIRCUITS

LTC2223 Datasheet(PDF) 21 Page - Linear Technology

LTC2223 Datasheet(HTML) 21 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL