LTC3879_15 datasheet(21/28 Pages) LINER

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LTC3879

3879f

inductor ripple current and load steps. The output voltage

ripple is given as:

ΔΔ

ESR

mmV

OUT RIPPLE

L MAX

()

(

)

.• .

()

51 45

However, a 0A to 10A load step will cause an output

change of up to:

ΔΔ

ESR

OUT STEP

LOAD

()

•.

()

4 5

Optional 2

× 47μF ceramic output capacitors are included

to minimize the effect of ESR and ESL in the output ripple

and to improve load step response.

PC Board Layout Checklist

The LTC3879 PC board layout can be designed with or

without a ground plane. A ground plane is generally pre-

ferred based on performance and noise concerns.

When using a ground plane, use a dedicated ground plane

layer. In addition, for high current it is recommended to

use a multilayer board to help with heat sinking power

components.

The ground plane layer should have no traces and be

as close as possible to the routing layer connecting the

power MOSFET’s.

Place LTC3879 Pins 9 to 16 facing the power compo-

nents. Keep components connected to Pin 1 close to

LTC3879 (noise sensitive components).

Place CIN, COUT, MOSFETs, DB and inductor all in one

compact area. It may help to have some components

on the bottom side of the board.

Use an immediate via to connect components to the

ground plane SGND and PGND of LTC3879. Use several

larger vias for power components.

Use compact switch node (SW) plane to improve cool-

ing of the MOSFETs and to keep EMI down.

Use planes for VIN and VOUT to maintain good voltage

ﬁltering and to keep power losses low.

Flood all unused areas on all layers with copper. Flooding

with copper will reduce the temperature rise of power

component. You can connect the copper areas to any

DC net. (VIN, VOUT, GND or to any other DC rail in your

system).

Place decoupling capacitor CC2 next to the ITH and SGND

pins with short, direct trace connections.

When laying out a printed circuit board without a ground

plane, use the following checklist to ensure proper op-

eration of the controller. These items are illustrated in

Figure 11.

Segregate the signal and power grounds. All small-signal

components should return to the SGND pin at one point.

SGND and PGND should be tied together underneath

the IC and then connect directly to the source of M2.

Place M2 as close to the controller as possible, keeping

the PGND, BG and SW traces short.

Keep the high dV/dT SW, BOOST and TG nodes away

from sensitive small-signal nodes.

Connect the input capacitor(s), CIN, close to the

power MOSFETs. This capacitor carries the MOSFET AC

current.

Connect the INTVCC decoupling capacitor CVCC closely

to the INTVCC and PGND pins.

Connect the top driver boost capacitor, CB, closely to

the BOOST and SW pins.

Connect the VIN pin decoupling CF closely to the VIN

and PGND pins.

APPLICATIONS INFORMATION

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