RT6296F datasheet(10/12 Pages) RICHTEK

10 / 12 page

RT6296F

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS6296F-00

May

2015

capacitor sized for the maximum RMS current should

be used. The RMS current is given by :

OUT

RMS

OUT(MAX)

OUT



This formula has a maximum at VIN = 2VOUT, where

IRMS = IOUT / 2. This simple worst-case condition is

commonly used for design because even significant

deviations do not offer much relief.

Choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to

meet size or height requirements in the design. The

selection of COUT is determined by the required

Effective Series Resistance (ESR) to minimize voltage

ripple. Moreover, the amount of bulk capacitance is

also a key for COUT selection to ensure that the control

loop is stable. Loop stability can be checked by viewing

the load transient response as described in a later

section. The output ripple,

VOUT, is determined by :

OUT

ESR

8fC





  







The output ripple will be highest at the maximum input

voltage since

IL increases with input voltage. Multiple

capacitors placed in parallel may be needed to meet

the ESR and RMS current handling requirement. Dry

tantalum, special polymer, aluminum electrolytic and

ceramic capacitors are all available in surface mount

packages. Special polymer capacitors offer very low

ESR value. However, it provides lower capacitance

density than other types. Although Tantalum capacitors

have the highest capacitance density, it is important to

only use types that pass the surge test for use in

switching

power

supplies.

Aluminum

electrolytic

capacitors have significantly higher ESR. However, it

can be used in cost-sensitive applications for ripple

current rating and long term reliability considerations.

Ceramic

capacitors

have

excellent

low

ESR

characteristics but can have a high voltage coefficient

and audible piezoelectric effects. The high Q of

ceramic capacitors with trace inductance can also lead

to significant ringing.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature.

The maximum power dissipation can be calculated by

the following formula :

PD(MAX) = (TJ(MAX) TA) / θJA

where TJ(MAX) is the maximum junction temperature,

TA is the ambient temperature, and θJA is the junction

to ambient thermal resistance.

For recommended operating condition specifications,

the maximum junction temperature is 125°C. The

junction to

ambient thermal resistance, θJA, is layout

dependent. For TSOT-23-8 (FC) package, the thermal

resistance, θJA, is 70°C/W on a standard four-layer

thermal test board. The maximum power dissipation at

TA = 25°C can be calculated by the following formula :

PD(MAX) = (125°C 25°C) / (70°C/W) = 1.428W for

TSOT-23-8 (FC) package

The maximum power dissipation depends on the

operating ambient temperature for fixed TJ(MAX) and

thermal

resistance, θJA. The derating curve in Figure 3

allows the designer to see the effect of rising ambient

temperature on the maximum power dissipation.

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