RT8130B datasheet(13/16 Pages) RICHTEK

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RT8130B

DS8130B-00

June 2015

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Figure 6 shows the system Bode plot. The close loop

gain is the sum of modulation gain and the compensation

gain. The modulation DC gain is determined by VIN/

ΔVOSC,

where

ΔVOSC is peak to peak voltage of the saw-tooth

ramp. In general, fZ1 is placed at half of fLC, and fZ2 is

placed at fLC to boost the large phase lag created by the

double pole especially when ESR is low. fP1 is typically

placed at fESR to obtain a

−20dB/dec slope at crossover

frequency. fP2 is placed at half of the switching frequency

to increase the attenuation in high frequency.

After calculating the compensation values, draw the

system Bode plot to check the crossover frequency and

phase margin. Due to the circuit parasitic components

and the characteristic deviation in the inductor and output

capacitors, further tuning of the compensation value to

obtain the required crossover frequency and phase margin

is necessary.

Figure 6. System Bode Plot

fLC

fESR

fZ1

(dB)

Freq.(Log)

Modulation Gain

Compensation Gain

Close Loop Gain

fZ2

fP2

fP1

fCROSS

Output voltage of the converter is scaled by the divider

resistors and then compared to the reference voltage, which

is the regulation level seen by the controller. The error

amplifier output voltage VCOMP is compared to the saw-

tooth waveform from the oscillator to generate PWM signal.

The output voltage is then regulated according to the duty

cycle of the PWM signal.



FB1

f, f

R2 R













f, f

2R2 C2











 





Figure 5. Type-III Compensator

VREF

VOUT

RFB1

RFB2

COMP

OUT

ESR

OUT

ESR











In order to obtain an accurate output voltage regulation

and fast transient response, a compensator is necessary.

Depending on the inductor and output capacitor, different

type of compensator can be used to finish the feedback

loop compensation. By inserting a well designed

compensator into the feedback loop, the closed loop

control-to-output transfer function can be shaped to have

adequate crossover frequency and sufficient phase margin.

The design goals are:



Obtain high gain at low frequency for DC regulation

accuracy



Obtain sufficient bandwidth for transient performance

(generally, 1/10 to 1/5 switching frequency)



Obtain sufficient phase margin for stability (generally

>45° )

Figure 5 shows the Type-III compensator, which is

composed of voltage error amplifier, impedance network

Z1 and Z2.

The system open loop gain

has two poles at

fLC and one zero at fESR. The frequency of fLC and fESR can

be calculated by the following expressions :

OUT

COMP

The Type-III compensator introduces three poles and two

zeros to the system. The first pole is located in low

frequency to increase the DC gain for voltage regulation

accuracy and is usually referred to as the pole at zero.

The location of rest of the two poles and two zeros can be

determined as follows :

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