58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

_______________________________________________________________________________________

5

by power-supply rejection test.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and

offset have been calibrated.

Note 3: Offset nullified.

Note 4: One sample is achieved every 18 clocks in continuous conversion mode.

Note 5: The track/hold acquisition time is two SCL cycles as illustrated in Figure 11.

Note 6: A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and

50ns in fast mode.

Note 8:

PSRR

V

(5.25V) - V

(4.75V)

2

V

5.25V - 4.75V

FS

FS

N

REF

=

where N is the number of bits (

).

14

t2

1

f

ACQ

SCL

=×









f

1 clocks

f

t

SAMPLE

SCL

C

-1

=+









8

ONV

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figure 1b and Figure 2)

Serial Clock Frequency

(Note 11)

1.7

MHz

Hold Time, (Repeated) Start

Condition

160

ns

Low Period of the SCL Clock

320

ns

High Period of the SCL Clock

120

ns

Setup Time for a Repeated

START Condition

160

ns

Data Hold Time

(Note 9)

0

150

ns

Data Setup Time

10

ns

Rise Time of SCL Signal

(Current Source Enabled)

(Note 10)

10

80

ns

Rise Time of SCL Signal After

Acknowledge Bit

(Note 10)

20

160

ns

Fall Time of SCL Signal

(Note 10)

20

80

ns

Rise Time of SDA Signal

(Note 10)

20

160

ns

Fall Time of SDA Signal

(Note 10)

20

160

ns

Setup Time for STOP Condition

160

ns

Capacitive Load for Each Bus Line

400

pF

Pulse Width of Spike Suppressed

10

ns