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5

ATS SERIES

(28V Input, Single/Dual Output)

1.

Parameter is tested as part of design characterization or after design changes. Thereafter, parameter shall

be guaranteed to the limits specified.

2.

Parameter verified during line and load regulation tests.

3.

Output load current must be distributed such that at least 20% of the total load current is being provided by

one of the outputs.

4.

Load current split equally between outputs on dual output models.

5.

Cross regulation is measured with 20% rated load on output under test while changing the load on the

other output from 20% to 80% of rated.

6.

Guaranteed for a D.C. to 20MHz bandwidth. Tested using a 20KHz to 10MHz bandwidth using the circuit

on page 6.

7.

Capacitive load may be any value from 0 to the maximum limit without compromising dc performance. A

capacitive load in excess of the maximum limit may interfere with the proper operation of the converter’s

overload protection, causing erratic behavior during turn-on.

8.

Overload power dissipation is defined as the device power dissipation with the load set such that V

90% of nominal.

9.

Load step transition time

≥ 10µs.

of its steady state value.

11. Line step transition time

≥ 100µs.

12. Turn-on delay time from either a step application of input power or a logic low to a logic high transition on

13. For operation at temperatures between +85

°C and +125°C, derate the maximum input voltage linearly from

100% to 75%.

Limits

Parameter

Group A

Subgroup

Conditions

-55

unless otherwise specified

Min

Nom

Max

Unit

Capacitive Load (CL)

ATS2803R3S

ATS2805S

ATS2812S

ATS2815S

ATS2805D

ATS2812D

ATS2815D

1

No effect on DC performance

Notes 1, 4, 7

Each output on duals

2200

1000

180

120

500

90

60

µF

Line Rejection

1

DC to 50KHz, Notes 1, 4

40

50

dB

Isolation

1

Input to Output or Any Pin to Case

except pin 3, test @ 500VDC

100

M

Ω

Device Weight

85

g

MTBF

MIL-HDBK-217F2, GM, 35

°C

1.0 X10

6

Hr