IR3448M datasheet(21/50 Pages) IRF

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IR3448

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June 18,. 2015

transitions to output voltage, a diode is recommended

to add between the external clock and Rt/Sync pin.

Figure 12 shows the timing diagram of these

transitions.

An internal circuit is used to change the PWM ramp

slope according to the clock frequency applied on

Rt/Sync pin. Even though the frequency of the

external synchronization clock can vary in a wide

range, the PLL circuit keeps the ramp amplitude

constant,

requiring

adjustment

the

loop

compensation. PVin variation also affects the ramp

amplitude, which will be discussed separately in Feed-

Forward section.

SYNC

...

Gradually change

Fs1

Fs2

Fs1

Free Running

Frequency

Synchronize to the

external clock

Return to free-

running freq

Gradually change

Figure 12: Timing Diagram for Synchronization

to the external clock (Fs1>Fs2 or Fs1<Fs2)

FEED-FORWARD

Feed-Forward (F.F.) is an important feature, because

it can keep the converter stable and preserve its load

transient performance when PVin varies. The PWM

ramp amplitude (Vramp) is proportionally changed

with PVin to maintain PVin/Vramp almost constant

throughout PVin variation range (as shown in Figure

13). The PWM ramp amplitude is adjusted to 0.15 of

PVin. Thus, the control loop bandwidth and phase

margin can be maintained constant. Feed-forward

function can also minimize impact on output voltage

from fast PVin change. F.F. is disabled when

PVin<6.2V and the PWM ramp is typically 0.9V. For

PVin<6.2V, PVin voltage should be accounted for

when calculating control loop parameters.

PVin

PWM Ramp

12V

Ramp Offset

21V

6.8V

12V

PWM Ramp

Amplitude = 1.8V

PWM Ramp

Amplitude = 3.15V

PWM Ramp

Amplitude = 1.02V

PWM Ramp

Amplitude =

0.15xPVin

Figure 13: Timing Diagram for Feed-Forward (F.F.)

Function

SMART LOW DROPOUT REGULATOR (LDO)

IR3448 has an integrated low dropout (LDO) regulator

which can provide gate drive voltage for both drivers.

In order to improve overall efficiency over the whole

load range, LDO voltage is set to 6.8V (typ.) at mid- or

heavy load condition to reduce Rds(on) and thus

MOSFET conduction loss; and it is reduced to 4.4V

(typ.) at light load condition to reduce gate drive loss.

The smart LDO selects its output voltage according to

the load condition by sensing the inductor current (IL).

At light load condition, the inductor current can fall

below zero as shown in Figure 14. A zero crossing

comparator is used to detect when the inductor

current falls below zero at the LDrv Falling Edge. If the

comparator detects zero crossing events for 256

consecutive switching cycles, the smart LDO reduces

its output to 4.4V. The LDO voltage will remain low

until a zero crossing is not detected. Once a zero

crossing is not detected, the counter is reset and LDO

voltage returns to 6.8V. Figure 14 shows the timing

diagram. Whenever the device turns on, LDO always

starts with 6.8V, then goes to 4.4V / 6.8V depending

upon the load condition.

However, if only Vin is

applied with Enable low, the LDO output is 4.4V.

Vcc/

LDO

256/Fs

...

6.8V

4.4V

...

Figure 14: Time Diagram for Smart LDO

IR3448M Datasheet(PDF) 21 Page - International Rectifier

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