AFBR-810BZ datasheet(3/48 Pages) AVAGO

3 / 48 page

Receiver Module

The optical receiver module (see Figure 2) incorporates

a 12-channel PIN photodiode array, a 12-channel pre-

amplifier and output buffer, diagnostic monitors, control

and bias blocks. The Rx Output Buffer provides CML

compatible differential outputs for the high speed elec-

trical interface presenting nominal single-ended output

impedances of 50 Ohms to AC ground and 100 Ohms

differentially that should be differentially terminated with

100 Ohms. DC blocking capacitors may be required. For

module control and interrogation, the control interface

(LVTTL compatible) incorporates a Two Wire Serial (TWS)

interface of clock and data signals and dedicated signals

for host interrupt, module address setting and module

reset. Diagnostic monitors for optical input power, tem-

perature, both supply voltages and elapsed operating

time are implemented and results are available through

the TWS interface.

Over the TWS interface, the user can, for individual

channels, control (flip) polarity of the differential outputs,

de-activate channels, disable the squelch function,

program output signal amplitude and de-emphasis

and change receiver bandwidth. A reset for the control

registers is available. Serial ID information and alarm

thresholds are provided. To reduce the need for polling,

the TWS interface is augmented with an interrupt signal

for the host.

Alarm thresholds are established for the monitored at-

tributes. Flags are set and interrupts generated when the

attributes are outside the thresholds. Flags are also set

and interrupts generated for loss of optical input signal

(LOS). All flags are latched and will remain set even if

the condition initiating the latch clears and operation

resumes. All interrupts can be masked and flags are reset

upon reading the appropriate flag register. The electri-

cal output will squelch for loss of input signal (unless

squelch is disabled) and channel de-activation through

TWS interface. Status and alarm information are available

via the TWS interface. The interrupt signal (selectable via

the TWS interface as a pulse or static level) is provided

to inform hosts of an assertion of an alarm and/or LOS.

Dout[11:0][p/n] (24)

IntL

SDA

SCL

Adr[2:0] (3)

ResetL

Vcc33 (4)

Vcc25 (2)

Gnd

Rx Output Buﬀer

12 Channels

Preamp

12 Channels

Control

Diagnostic Monitors

Bias

Figure 2. Receiver Block Diagram

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