7 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS

6

REVISION C 04/22/15

9DBU0741 DATASHEET

Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating

Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Supply Voltage

VDDx

Supply voltage for core and analog

1.425

1.5

1.575

V

Output Supply Voltage

VDDIO

Low Voltage Supply LP-HCSL Outputs

0.95

1.05-1.5

1.575

V

Commmercial range

0

25

70

°C

1

Industrial range

-40

25

85

°C

1

Input High Voltage

Single-ended inputs, except SMBus

V

Input Mid Voltage

Single-ended tri-level inputs ('_tri' suffix)

V

Input Low Voltage

Single-ended inputs, except SMBus

-0.3

V

-5

5

uA

Single-ended inputs

-200

200

uA

Input Frequency

1

167

MHz

2

Pin Inductance

7nH

1

Logic Inputs, except DIF_IN

1.5

5

pF

1

DIF_IN differential clock inputs

1.5

2.7

pF

1,5

Output pin capacitance

6

pF

1

Clk Stabilization

stabilization or de-assertion of PD# to 1st clock

1ms

1,2

Input SS Modulation

Frequency PCIe

Allowable Frequency for PCIe Applications

(Triangular Modulation)

30

33

kHz

Input SS Modulation

Frequency non-PCIe

Allowable Frequency for non-PCIe Applications

(Triangular Modulation)

066

kHz

OE# Latency

DIF start after OE# assertion

DIF stop after OE# deassertion

1

3

clocks

1,3

Tdrive_PD#

DIF output enable after

PD# de-assertion

300

us

1,3

Tfall

Fall time of single-ended control inputs

5

ns

2

Trise

Rise time of single-ended control inputs

5

ns

2

SMBus Input Low Voltage

0.6

V

SMBus Input High Voltage

2.1

3.3

V

4

SMBus Output Low Voltage

0.4

V

SMBus Sink Current

4mA

Nominal Bus Voltage

Bus Voltage

1.425

3.3

V

SCLK/SDATA Rise Time

(Max VIL - 0.15) to (Min VIH + 0.15)

1000

ns

1

SCLK/SDATA Fall Time

(Min VIH + 0.15) to (Max VIL - 0.15)

300

ns

1

SMBus Operating

Frequency

Maximum SMBus operating frequency

400

kHz

6

Input Current

Capacitance

Ambient Operating

Temperature