2-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR

6

REVISION A 07/17/15

9FGL02 DATASHEET

Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating

Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Supply Voltage

VDDxxx

Supply voltage for core, analog and single-ended

LVCMOS outputs.

3.135

3.3

3.465

V

IO Supply Voltage

VDDIO

Supply voltage for differential Low Power outputs.

0.9975

1.05-3.3

3.465

V

Commmercial range

0

25

70

°C

Industrial range

-40

25

85

°C

Input High Voltage

Single-ended inputs, except SMBus

V

Input Mid Voltage

Single-ended tri-level inputs ('_tri' suffix)

V

Input Low Voltage

Single-ended inputs, except SMBus

-0.3

V

-5

5

uA

Single-ended inputs

-200

200

uA

Input Frequency

XTAL, or X1 input

8

25

40

MHz

4

Pin Inductance

7nH

1

Logic Inputs, except DIF_IN

1.5

5

pF

1

Output pin capacitance

6

pF

1

Clk Stabilization

stabilization or de-assertion of PD# to 1st clock

0.35

1.8

ms

1,2

SS Modulation Frequency

Allowable Frequency

(Triangular Modulation)

30

31.6

33

kHz

1

OE# Latency

DIF start after OE# assertion

DIF stop after OE# deassertion

1

3

clocks

1,3

Tdrive_PD#

DIF output enable after

PD# de-assertion

300

us

1,3

Tfall

Fall time of single-ended control inputs

5

ns

1,2

Trise

Rise time of single-ended control inputs

5

ns

1,2

Input Current

Ambient Operating

Temperature

Capacitance