Data Sheet #: SG084

Page 4 of 14

Rev: 00

Date: 09/08/04

Output Jitter Specifications

Table 6

Jitter BW 10 Hz - 20 MHz

SONET Jitter BW 12 kHz - 20 MHz

Frequency (MHz)

pS (RMS)

m UI

pS (RMS)

m UI

155.52 (PECL)

10(typical)

1.55 (typical)

1 (max)

0.156 (max)

77.76 (PECL)

10(typical)

0.77 (typical)

1 (max)

0.077 (max)

77.76 (CMOS)

15(typical)

1.16 (typical)

3 (max),0.4 (typical)

0.467 (max)

LVPECL Output Characteristics

Table 5

Symbol

Parameter

Minimum

Nominal

Maximum

Units

Notes

f

OUT

Available LVPECL Output Frequencies

4.86

155.52

MHz

3

V

OH

High Level LVPECL Voltage

V

-

V

V

V

OL

Low Level LVPECL Voltage

V

-

V

V

C

L

Output Capacitance

3

pF

T

SKEW

Differential Output Skew

280

ps

T

Rise/Fall Time (20%-80%)

0.35

1

ns

DC

Positive Duty Cycle

45

55

%

I

SAVINGS

Current Savings per Unloaded PECL Pair

20

mA

CMOS Input And Output Characteristics

Table 4

Symbol

Parameter

Minimum

Nominal

Maximum

Units

Notes

f

OUT

Available CMOS Output Frequencies

8 k

155.52 M

Hz

3

V

IH

High Level Input Voltage

2

5.5

V

V

IL

Low Level Input Voltage

0

0.8

V

T

IO

I/O to Output Valid

10

nS

C

O

Output Capacitance

10

pF

V

HO

High Level Output Voltage loh = 04mA

2.4

Vcc Min.

V

IO

Low Level Output Voltage lo1 = 6mA

0.5

Vcc Max.

T

IR

Input Reference Signal Pulse Width

12.5

nS

DC

Positive Duty Cycle

40

60

%

4

NOTES:

3.0: Refer to the available frequency combination table in the Ordering Information Section on page 8.

4.0: If the CMOS output is an even divide of Y0, then its duty cycle will be ~50%.

Control 1

(Pin 19)

Control 2

(Pin 20)

Description

0

0

Unit is locked to Reference A

0

1

Unit is locked to Reference B

1

0

Unit is forced into Free Run

1

1

Outputs are in Tri-State

Control Table

Table 7