Data Sheet #: SG032

Page 2 of 12

Rev: P01

Date: 12/11/ 02

Absolute Maximum Rating

Table 1

Symbol

Parameter

Minimum

Nominal

Maximum

Units

Notes

V

CC

Power Supply Voltage

-0.5

4

Volts

1

V

I

Input Voltage

-0.5

5.5

Volts

1

T

S

Storage Temperature

-65

150

deg. C

1

General Description

The SCG3050 is a mixed signal phase locked loop

generating 155.52 MHz LVPECL outputs from an

intrinsically low jitter voltage controlled crystal oscillator.

The SCG3050 is phase locked to an external 8 kHz

reference input. The SCG3050 is ideal for applications

using multiplication to obtain higher SONET frequencies.

The package dimensions are 0.75" x 1.25" x .45" on

a 6 layer, designed impedence, FR4 board with

castellated pins. Parts are assembled using high

temperature solder to withstand surface mount reflow

processes. See Fig. 4 for the solder profile.

Functional Block Diagram

Figure 1

Filter

LVPECL

Driver

Low

Jitter

VCXO

Divider

REF

Q1

QN1

Q2

QN2