where:

ground

power-line voltage

For this application circuit, a 10% margin is reason-

able, so the value used is 50k

Ω. This gives a maxi-

mum duty cycle of 50%. The maximum duty cycle

can now be expressed as:

where:

comparator

0.5V and 2.5V are the values at the beginning and

end of the PWM ramp.

for clock frequency variation. If the clock is running

at 300kHz and the input voltage is fixed, then the

duty cycle is a scaled portion of the maximum duty

7) Low-ESR/ESL ceramic capacitors were used in this

application. The output filter is made by two 22µF

ceramic capacitors in parallel. Normally, the ESR of

a capacitor is a dominant factor determining the rip-

ple, but in this case it is the capacitor value.

Calculating

the ripple will be a fraction of this depending on the

duty cycle. For a 50% duty cycle, the ripple due to

the capacitance is approximately 45mV.

8)The PWM gain can be calculated from:

Note that while the above formula incorporates the

Ω), the

Ω),

the gain is multiplied by the square root of 10 and

becomes +10V/V. The pole of the system due to the

output filter is 1 / 2

πRC, where R is the load resis-

tance and C the filter capacitor. Choosing a capaci-

tor and calculating the pole frequency by:

it is 723Hz at full load. At 10% load it will be 72Hz,

since the load resistor is then 50

Ω instead of 5Ω. The

total loop gain is equal to the PWM gain times the

gain in the combination of the voltage divider and

the error amplifier. The worst case for phase margin

is at full load. For a phase margin of 60 degrees, this

midband gain (G) must be set to be less than:

where:

PM = Phase margin angle

The DC accuracy of the regulator is a function of the

DC gain. For 1% accuracy, a DC gain of 20 is required.

Since the maximum midband gain for a stable

response is 16, an integrator with a flat midband gain

given by a zero is used. The midband gain is less than

16, to preserve stability, and the DC gain is much larger

than 20, to achieve high DC accuracy.

Optimization on the bench showed that a midband gain

of 5 gave fast transient response and settling with no

ringing. The zero was pushed as high in frequency as

possible without losing stability. The zero must be a

factor of two or so below the system unity-gain frequen-

cy (crossover frequency) at minimum load. With the

G

PM A

MHz

Hz

UErrorAmp

PWM

P

tan(

)

.

<

ƒ

ƒ

=

⋅⋅

⋅ ⋅

1

1 7 3 723

ƒ=









=









⋅⋅

⋅ ⋅

P

LL

RC

F

1

2

1

25

44

ππ

µ

Ω

A

dV

dV

R

2L

V

2.0V

R

2L

PWM

OUT

CON

L

PRI

SW

MIN

L

PRI

SW

==

ƒ









=

ƒ









≅

⋅⋅

⋅⋅

.

%

()

DC

V

V

MAX VMIN

36

20

50

3

I

C

A

kHz

F

mV

OUT

SW

ƒ

==

⋅⋅

1

300

44

76

µ

DC(V

,V

) =

V

0.5V

2.0V

50%

DC(V

,V

)

V

0.5V

2.0V

25%

DC(2.5V,V

)

50%

DC(2.5V,V

)

25%

DC(0.5V,V

)

0

DC(0.5V,V

)

0

CON MIN

CON

CON MAX

CON

MIN

MAX

MIN

MAX

−









=

−









=

=

=

=

DC(V

)

V

0.5V

2.0V

V

V

DC

V

- 0.5V

2.0V

36V

V

50%

CON,VIN

CON

MIN

IN

NOM

MAX(VMIN)

CON

IN

SW

NOM

=

−

















ƒ

ƒ









≈ 















ƒ

ƒ









⋅

SW

High-Voltage PWM

Power-Supply Controller

14

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