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S93C46B Datasheet(PDF) 21 Page - Seiko Instruments Inc

Part # S93C46B
Description  FOR AUTOMOTIVE 105C OPERATION
PDF  34 Pages
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Manufacturer  SII [Seiko Instruments Inc]
Direct Link  http://www.sii.co.jp
Logo SII - Seiko Instruments Inc

S93C46B Datasheet(HTML) 21 Page - Seiko Instruments Inc

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FOR AUTOMOTIVE 105
°C OPERATION 3-WIRE SERIAL E
2PROM
Rev.2.1_00
S-93C46B/56B/66B H Series
Seiko Instruments Inc.
21
3-Wire Interface (Direct Connection between DI and DO)
There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI, and DO pins,
and a 3-wire interface that connects the DI input pin and DO output pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the
serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins
of the S-93C46B/56B/66B via a resistor (10 to 100 k
Ω) so that the data output from the CPU takes precedence in being
input to the DI pin (refer to “Figure 20 Connection of 3-Wire Interface”).
CPU
DI
SIO
DO
S-93C46B/56B/66B
R : 10 to 100 k
Ω
Figure 20 Connection of 3-Wire Interface
I/O Pin
1. Connection of input pins
All the input pins of the S-93C46B/56B/66B employ a CMOS structure, so design the equipment so that high
impedance will not be input while the S-93C46B/56B/66B is operating. Especially, deselect the CS input (a low
level) when turning on/off power and during standby. When the CS pin is deselected (a low level), incorrect data
writing will not occur. Connect the CS pin to GND via a resistor (10 to 100 k
Ω pull-down resistor). To prevent
malfunction, it is recommended to use equivalent pull-down resistors for pins other than the CS pin.
2. Equivalent circuit of input and output pin
The following shows the equivalent circuits of input pins of the S-93C46B/56B/66B. None of the input pins
incorporate pull-up and pull-down elements, so special care must be taken when designing to prevent a floating
status.
Output pins are high-level/low-level/high-impedance tri-state outputs. The TEST pin is disconnected from the
internal circuit by a switching transistor during normal operation. As long as the absolute maximum rating is
satisfied, the TEST pin and internal circuit will never be connected.



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