LPC18S5X_15 datasheet(77/152 Pages) PHILIPS

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LPC18S5X_S3X

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Product data sheet

Rev. 1 — 24 February 2015

77 of 152

NXP Semiconductors

LPC18S5x/S3x

32-bit ARM Cortex-M3 microcontroller

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48,

96, 192) kHz.

• Support for an audio master clock.

• Configurable word select period in master mode (separately for I2S-bus input and

output).

• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. The DMA requests are

connected to the GPDMA block.

• Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus

output.

7.16.6 C_CAN

Remark: The LPC18S5x/S3x contain two C_CAN controllers.

Controller Area Network (CAN) is the definition of a high performance communication

protocol for serial data communication. The C_CAN controller is designed to provide a full

implementation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller can build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a high level of reliability.

7.16.6.1

Features

• Conforms to protocol version 2.0 parts A and B.

• Supports bit rate of up to 1 Mbit/s.

• Supports 32 Message Objects.

• Each Message Object has its own identifier mask.

• Provides programmable FIFO mode (concatenation of Message Objects).

• Provides maskable interrupts.

• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN

applications.

• Provides programmable loop-back mode for self-test operation.

7.17 Counter/timers and motor control

7.17.1 General purpose 32-bit timers/external event counter

Remark: The LPC18S5x/S3x include four 32-bit timer/counters.

The timer/counter is designed to count cycles of the system derived clock or an externally

supplied clock. It can optionally generate interrupts, generate timed DMA requests, or

perform other actions at specified timer values, based on four match registers. Each

timer/counter also includes two capture inputs to trap the timer value when an input signal

transitions, optionally generating an interrupt.

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