CMX7164 datasheet(21/146 Pages) CMLMICRO

21 / 146 page

CMX7164 Multi Mode Modem

CMX7164

 2015 CML Microsystems Plc

Page 21

D/7164_FI-1.x/FI-2.x/FI-4.x/FI-6.x/22

5.3

I/Q Output Reconstruction Filter

The CMX7164 I/Q Outputs provide internal reconstruction filtering with four selectable bandwidths (-3dB

point shown in section 13.1.22). The bandwidth of the internal reconstruction filter may be selected using

the I/Q Output Configuration - $B3 write or Signal Control - $61 write registers.

To complete the I/Q output reconstruction filter one of the following external RC networks should be used

for each of the differential outputs. The external RC network should have a bandwidth that matches the

bandwidth of the selected internal reconstruction filter.

Bandwidth (kHz)

R3-R6 (kOhms)

C9-C10 (pF)

100

150

12.5

270

Figure 10 Recommended External Components

– I/Q Output Reconstruction Filter

When transmitting an I/Q signal, each I/Q output will produce a signal with bandwidth half the channel

bandwidth. A reconstruction filter with a

–3dB point close to half the channel bandwidth will therefore have

significant roll off within the channel bandwidth

– which is undesirable. An appropriate choice for channels

occupying up to a 25kHz bandwidth (channel bandwidth/2 = 12.5kHz) would be a reconstruction filter of

25kHz bandwidth.

5.4

I/Q Input Antialias Filter

The device has a programmable antialias filter in the I/Q input path, which is controlled using the I/Q Input

Configuration - $B0 write or Signal Control - $61 write registers. This should be sufficient for most

applications, however if additional filtering is required it can be done at the input to the device.

The input impedance of the I/Q Input pins varies with the input gain setting, see section 12.1.3 Operating

Characteristics.

5.5

GPIO Pins

All GPIO pins are configured as inputs with an internal bus-hold circuit, after the Function

Image™ has

been loaded. This avoids the need for users to add external termination (pullup/pulldown) resistors onto

these inputs. The bus-

hold is equivalent to a 75kΩ resistor either pulling up to logic 1 or pulling down to

logic 0. As the input is pulled to the opposite logic state by the user, the bus-hold resistor will change, so

that it also pulls to the new logic state. The internal bus-hold can be disabled or re-enabled using

programming register P1.20 in Program Block 1

– Clock Control.

If the device is reset (either by asserting RESETN pin 7, issuing a C-BUS General RESET or by triggering

an internal power on reset) all GPIO pins will be immediately configured as inputs. Any GPIO pins not

being pulled either up or down by an external load will be left in a floating state until the Function Image

is loaded. To avoid GPIO floating input states that may somewhat elevate supply current between a

RESET and Function Image

TM load, it will be necessary to connect pull up or pull down resistors of 220k



to these pins.

CMX7164 Datasheet(PDF) 21 Page - CML Microcircuits

CMX7164 Datasheet(HTML) 21 Page - CML Microcircuits

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL