ZL2102ALAFTK datasheet(9/58 Pages) INTERSIL

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ZL2102

FN8440.2

November 20, 2014

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Power Conversion Overview

The ZL2102 operates as a voltage-mode, synchronous buck

converter with a selectable constant frequency pulse width

modulator (PWM) control scheme. The ZL2102 integrates dual

low rDS(ON) synchronous MOSFETs and a high-side driver to

minimize the circuit footprint. Figure 8 illustrates the basic

synchronous buck converter topology showing the primary power

train components. This converter is also called a step-down

converter, as the output voltage must always be lower than the

input voltage.

The ZL2102 integrates two N-channel power MOSFETs; QH is the

top control MOSFET and QL is the bottom synchronous MOSFET.

The amount of time that QH is on as a fraction of the total

switching period is known as duty cycle D, which is described by

Equation 1:

During time D, QH is on and VIN to VOUT is applied across the

inductor. The output current ramps up as shown in Figure 9.

When QH turns off (time 1-D), the current flowing in the inductor

must continue to flow from the ground up through QL, during

which the current ramps down. Since the output capacitor COUT

exhibits low impedance at the switching frequency, the AC

component of the inductor current is filtered from the output

voltage so the load sees nearly a DC voltage.

The maximum conversion ratio is shown in Figure 7. Typically,

buck converters specify a maximum duty cycle that effectively

limits the maximum output voltage that can be realized for a

given input voltage and switching frequency. This duty cycle limit

ensures that the low-side MOSFET is allowed to turn on for a

minimum amount of time during each switching cycle, which

enables the bootstrap capacitor to be charged up and provide

adequate gate drive voltage for the high-side MOSFET.

The block diagram for the ZL2102 is illustrated in Figure 2. In

this circuit, the target output voltage is regulated by connecting

the VSEN pin directly to the output regulation point. The VSEN

signal is then compared to an internal reference voltage that had

been set to the desired output voltage level by the user. The error

signal derived from this comparison is converted to a digital

value with an analog-to-digital (A/D) converter. The digital signal

is also applied to an adjustable digital compensation filter and

the compensated signal is used to derive the appropriate PWM

duty cycle for driving the internal MOSFETs in a way that

produces the desired output.

Power Management Overview

The ZL2102 incorporates a wide range of configurable power

management features that are simple to implement with no

external components. Additionally, the ZL2102 includes circuit

protection features that continuously safeguard the device and

load from damage due to unexpected system faults. The ZL2102

can continuously monitor input voltage, output voltage/current,

and internal temperature. A power-good output signal is also

included to enable power-on reset functionality for an external

processor.

All power management functions can be configured using either

pin configuration techniques described in this document or via

the SMBus interface using PMBus commands. Monitoring

parameters can also be preconfigured to provide alerts for

specific conditions. “PMBus Command Summary” on page 19

contains a listing of all the PMBus commands supported by the

ZL2102 and a detailed description of the use of each of these

commands.

Functional Description and Configuration

INTERNAL BIAS REGULATORS AND INPUT SUPPLY

CONNECTIONS

The ZL2102 employs three internal LDO regulators, allowing

operation from a single input supply from 4.5V to 14V. The

regulators are as follows:

• VR is derived from VDDS and provides a 7V bias supply for the

internal high-side MOSFET driver circuit. A 4.7µF capacitor is

required for the VR pin.

• VRA is derived from VDDS and provides a 5V bias supply for

the internal analog circuitry. A 4.7µF capacitor is required for

the VR pin.

• V2P5 is derived from VRA and provides a 2.5V bias supply for

the digital circuitry. A 10µF capacitor is required at the V2P5

pin.

VIN

VOUT

COUT

ZL2102

CIN

PWM

LDO

FIGURE 8. STEP DOWN CONVERTER

OUT

----------------



(EQ. 1)

TIME

VIN - VOUT

-VOUT

1 - D

ILPK

ILV

FIGURE 9. OUTPUT CURRENT

ZL2102ALAFTK Datasheet(PDF) 9 Page - Intersil Corporation

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