DATA REGISTER SPI TRANSFERS

CONFIGURATION REGISTER SPI TRANSFERS

The SEL pin is used to select between SPI transfers to/from the

Data Register or Configuration Regster. When SEL is high, the

Data Register path is selected for the transfer, as follows:

When

goes low, the output of each sensor is latched into the

Data Register and DR8 is output at SO. The next 7 rising edges

of SCK shift out Data Register bits 7 through 1. Simultaneously,

data presented at SI is shifted into the Data Register, DR8 is

written on the first rising edge of SCK and DR1 on the eight SCK

rising edge. The eighth SCK edge also causes the new DR8

value to be output at SO (see figure 10). This data transfer

method allows multiple HI-8428-R devices to be “daisy-

chained” such that the Data Registers from each device are

cascaded to form a single shift register. Figure 15 shows a

typical configuration of three daisy-chained HI-8428-Rs to form

a 24-input sensor. Note that when reading from more than one

device,

must remain low throughout the data read

sequence. Taking

high and then low again between eight-bit

reads will cause the sensor data to be re-latched into the Data

Registers, overwriting data shifted in from earlier HI-8428-Rs in

the chain. See Figure 11 for an example of a 24-bit Data

Register read operation.

CS

CS

CS

The SEL pin is held low for SPI accesses to the Configuration

Register. Write / read timing is identical to Data Register

transfers, except with the added complication that the

Configuration Register is nine bits rather than eight bits. Care

should be taken to ensure correct bit alignment when shifting

data into and out of the register, particularly when daisy-

chaining multiple devices. Figures 12 - 14 show examples of a

single 9-bit transfer, padded 16-bit transfer and daisy-

chained18-bit transfer.

SI8

DR8

High Z

High Z

CS

SO

SI

SCK (SPI Mode 0)

Figure 10. Single-Byte Data Register Read

SERIAL PERIPHERAL INTERFACE

The HI-8428-R uses a SPI (Serial Peripheral Interface) for host

access to the internal Configuration and Data Registers which

program the sensor mode and store sensor status. Host serial

communication is enabled through the active low, Chip Select

(

) pin, and is accessed via a four-wire interface consisting of

Serial Data Input (SI) from the host, Serial Data Output (SO) to

the host, the Serial Clock (SCK) and the

. All read / write

cycles are completely self-timed.

The SPI protocol specifies master and slave operation; the

HI-8428-R operates as a SPI slave.

T

As seen in Figure 10, SPI Mode 0 holds SCK in the low state

when idle. The SPI protocol transfers serial data in 8-bit bytes.

Once

is asserted, the rising edge of SCK shifts the input

data into the slave devices, starting with each byte's most-

significant bit. A rising edge on

completes the serial transfer

and re-initializes the HI-8428-R SPI for the next transfer. If

goes high before a full byte is clocked by SCK, the incomplete

byte clocked into the device will be latched.

Both master and slave simultaneously send and receive serial

data (full duplex), per Figure 10 below. The HI-8428-R

maintains high impedance on the SO output whenever

is

high.

The maximum SCK frequency is 10MHz. The HI-8428-R logic

is fully static and therefore there is no minimum SCK speed.

CS

CS

CS

CS

CS

he SPI protocol defines two parameters, CPOL (clock

polarity) and CPHA (clock phase). The possible CPOL-CPHA

combinations define four possible “SPI Modes”. The HI-8428-R

operation is based on Mode 0 (CPHA = 0, CPOL = 0), where

input data for each device is clocked on the rising edge of SCK,

but data is also clocked out on the positive edge, see figure 10.

CS

HOLT INTEGRATED CIRCUITS

7

SEL

VALID

SENSEn

DR7

DR6

DR5

DR4

DR3

DR2

DR1

SI8

FUNCTIONAL DESCRIPTION (cont.)

HI-8428-R

Data is shifted out of Data Register on rising edge of SCK

Sensor state is latched into Data Register on falling edge of CS