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SY100S317FC Datasheet(PDF) 1 Page - Micrel Semiconductor

Part # SY100S317FC
Description  TRIPLE 2-WIDE OA/OAI GATE
PDF  5 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY100S317FC Datasheet(HTML) 1 Page - Micrel Semiconductor

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SY100S317
TRIPLE 2-WIDE
OA/OAI GATE
DESCRIPTION
The SY100S317 is a set of ultra-fast, triple 2-wide OR/
AND gates designed for use in high-performance ECL
systems. This device offers both true and complement
outputs. The inputs on this device have 75K
Ω pull-down
resistors.
s Max. propagation delay of 900ps
s IEE min. of –48mA
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75K
Ω input pull-down resistors
s Approximately 40% lower power than Fairchild
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
FEATURES
Rev.: G
Amendment: /0
Issue Date:
July, 1999
BLOCK DIAGRAM
D1a
Oa
Oa
D2a
D3a
D4a
Ea
D1b
Ob
Ob
D2b
D3b
D4b
Eb
D1c
Oc
Oc
D2c
D3c
D4c
Ec
Pin
Function
Dna – Dnc
Data Inputs (n = 1...4)
Ea – Ec
Enable Inputs
Oa – Oc
Data Outputs
Oa – Oc
Complementary Data Outputs
VEES
VEE Substrate
VCCA
VCCO for ECL Outputs
PIN NAMES
PIN CONFIGURATIONS
D4a
D3a
D2a
D1a
Oa
Oa
D3b
D1c
D3c
D4b
D4c
D2c
18
17
16
15
14
13
1
2
3
4
5
6
7
24
8
23
9
22
10
21
11
20
12
19
Top View
Flatpack
F24-1
Ob
Ob
VCCA
VCC
Oc
VCC
Ea
VEE
Ec
Eb
D1b
VEES
4
3
2
1
28
27
12
13
14
15
16
17
19
11
20
10
21
9
22
8
23
7
24
6
Top View
PLCC
J28-1
Oc
D2b
26
18
25
5
1


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