© 1996 Microchip Technology Inc.

DS11183D-page 3

24C01A/02A/04A

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Min.

Typ

Max.

Units

Remarks

Clock frequency

—

—

100

kHz

Clock high time

4000

—

—

ns

Clock low time

4700

—

—

ns

SDA and SCL rise time

—

—

1000

ns

SDA and SCL fall time

—

—

300

ns

START condition hold time

4000

—

—

ns

After this period the first

clock pulse is generated

START condition setup time

4700

—

—

ns

Only relevant for repeated

START condition

Data input hold time

0—

—

ns

Data input setup time

250

—

—

ns

Data output delay time

300

—

3500

(Note 1)

STOP condition setup time

4700

—

—

ns

Bus free time

4700

—

—

ns

Time the bus must be free

before a new transmission

can start

Input filter time constant

(SDA and SCL pins)

—

—

100

ns

Program cycle time

—

.4

1

ms

Byte mode

.4N

N

ms

Page mode, N=# of bytes

Endurance

—

1M

—

—

cycles

25

°C, Vcc = 5.0V, Block

Mode (Note 2)

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

SCL

SDA

IN

SDA

OUT