24LCS61/62

© 1997 Microchip Technology Inc.

Preliminary

DS21226A-page 13

9.0

EXTERNAL DEVICE SELECT

(EDS) PIN AND OUTPUT

ENABLE (OE) BIT

The External Device Select (EDS) pin is an open drain,

low active output and may be used by the system

designer for functions such as enabling other circuitry

when the 24LCS61/62 is being accessed. Because the

pin is an open drain output, a pull-up resistor is required

for proper operation of this pin. When the device is pow-

ered up, the EDS pin will always be in the high imped-

ance state (off). The EDS pin function is controlled by

using the output enable (OE) bit in the control byte of

each command. If the OE bit is high, the EDS pin is

enabled and if the OE bit is low the pin is disabled. For

the Assign Address command and standard read or

write commands, the EDS pin will pull low (providing

that the OE bit is set high) on the rising clock edge after

the ack bit following the ID byte. See Figure 9-1. For

commands such as the Clear Address command, the

EDS pin will change states at the rising clock edge just

before the Stop bit. It is also possible to control the EDS

pin by sending a partial command such as the control

byte and ID byte for a write command followed by the

Stop bit. The EDS pin would change states just before

the Stop bit as shown in the lower portion of Figure 9-

1. When the EDS pin has changed states, it is latched

and will remain in a given state until another command

is sent to the device with the OE bit set to change the

state of the pin, or power to the device is removed.

FIGURE 9-1:

EDS PIN OPERATION

SCL

9

8

7

6

5

4

3

2

1

123

For commands such as the Assign Address command or standard read and

writes, the EDS pin will be asserted on this rising clock edge if the OE bit was set

to a one in the control byte. If the OE bit is a zero and the previous command

asserted it, then the EDS pin will be released by the device on this clock edge.

SDA

9

8

7

6

51

2

3

0

1

1

0

Start

Bit

Control

Byte

ACK

BIT

4

ID Byte

ACK

BIT

SCL

9

8

7

6

5

4

3

2

1

123

For commands such as the Clear Address command, the command is ter-

minated at this point with a STOP bit. The EDS pin will be asserted on this

rising clock edge if the OE bit was set to a one in the control byte. If the OE

bit is a zero and the previous command asserted it, then the EDS pin will be

released by the device at this point.

SDA

9

8

7

6

5

0

1

1

0

Start

Bit

Control

Byte

ACK

BIT

4

ID Byte

ACK

BIT

STOP

BIT

EDS

EDS