PIC16C642-04SLASHP datasheet(69/136 Pages) MICROCHIP

69 / 136 page

Preliminary

DS30559A-page 69

PIC16C64X & PIC16C66X

9.7

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator which does not require any external com-

ponents. The block diagram is shown in Figure 9-17.

This RC oscillator is separate from the RC oscillator of

the OSC1/CLKIN pin. This means that the WDT will

run, even if the clock on the OSC1 and OSC2 pins has

been stopped, for example, by execution of a SLEEP

instruction. During normal operation, a WDT time-out

generates a device RESET. If the device is in SLEEP

mode, a WDT time-out causes the device to wake-up

and continue with normal operation, this is known as a

WDT wake-up. The WDT can be permanently disabled

by clearing conﬁguration bit WDTE (Section 9.1).

9.7.1

WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out period varies with temper-

ature, VDD and process variations from part to part (see

DC specs). If longer time-outs are desired, a prescaler

with a division ratio of up to 1:128 can be assigned to

the WDT, under software control, by writing to the

OPTION register. Thus, time-out periods of up to 2.3

seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT and

the postscaler (if assigned to the WDT) and prevent it

from timing out and generating a device RESET.

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer time-out (WDT Reset and WDT

wake-up).

9.7.2

WDT PROGRAMMING CONSIDERATIONS

It should also be taken in account that under worst case

conditions (VDD = Min., Temperature = Max., max.

WDT prescaler) it may take several seconds before a

WDT time-out occurs.

Note:

When the prescaler is assigned to the

WDT, always execute a CLRWDT instruction

before changing the prescale value, other-

wise a WDT reset may occur.

FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM

FIGURE 9-18: SUMMARY OF WATCHDOG TIMER REGISTERS

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2007h

Conﬁg. bits

MPEEN

BODEN(1)

CP1

CP0

PWRTE(1)

WDTE

FOSC1

FOSC0

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Figure 9-1 for details of the operation of these bits.

From TMR0 Clock Source

(Figure 7-6)

To TMR0 (Figure 7-6)

Postscaler

WDT Timer

WDT

Enable Bit

PSA

8 - to - 1 MUX

PS2:PS0

MUX

PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION register.

PIC16C642-04/P Datasheet(PDF) 69 Page - Microchip Technology

PIC16C642-04/P Datasheet(HTML) 69 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL