PIC16HV540

DS40197A-page 4

Preliminary

© 1998 Microchip Technology Inc.

3.0

ARCHITECTURAL OVERVIEW

FIGURE 3-1:

PIC16HV540 BLOCK DIAGRAM

This section provides information on the architecture of the PIC16HV540. For information on operation of the periph-

erals, electrical specifications, etc., please refer to the PIC16C5X data sheet (DS30453).

WDT

TIME

OUT

8

STACK 1

EPROM

512 X 12

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

WATCH-

DOG

CONFIGURATION WORD

OSCILLATOR/

TIMING &

CONTROL

GENERAL

PURPOSE

REGISTER

FILE

(SRAM)

25 Bytes

WDT/TMR0

PRESCALER

OPTION

“OPTION”

“SLEEP”

“CODE

PROTECT”

“OSC

SELECT”

DIRECT ADDRESS

TMR0

FROM W

FROM W

“TRIS 5”

“TRIS 6”

FSR

TRISA

PORTA

TRISB

PORT

T0CKI

PIN

9-11

9-11

12

12

8

W

4

4

4

DATA BUS

8

8

8

8

ALU

STATUS

FROM W

CLKOUT

8

9

6

5

5-7

OSC1 OSC2 MCLR

PC

“DISABLE”

2

RA3:RA0

RB7:RB0

DIRECT RAM

ADDRESS

8

HIGH VOLTAGE

TRANSLATION

3V/5V

Regulator

VDD

STACK 2

STACK 3

STACK 4

“TRIS 7”

FROM W

6

OPTION2

3V/5V

Regulator

BOD

BL/BE

RL/SL

PC

(PIN CHANGE)

WPC

4

RB3 : RB0

FILTER

RB7

SWE (OPTION2 REGISTER)