LP2992

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SNVS171H – NOVEMBER 2001 – REVISED JANUARY 2015

7 Detailed Description

7.1 Overview

The LP2992 family of fixed-output, ultralow-dropout, and low-noise regulators offer exceptional and cost-effective

performance for battery-powered applications. Available in output voltages from 1.5 V to 5 V, the family has an

output tolerance of 1% for the A version and capable of delivering 250-mA continuous load current. Using an

optimized VIP (Vertically Integrated PNP) process, the LP2992 delivers unequaled performance. The dropout

voltage and the ground pin current with 250 mA of load current are typically 450 mV and 1500 µA, respectively.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Sleep Mode

When the ON/OFF pin is pulled low, the LP2992 enters a sleep mode, and less than 1-µA quiescent current is

consumed. This function is designed for the application which needs a sleep mode to effectively enhance battery

life cycle.

7.3.2 Low Ground Current

The LP2992 uses a vertical PNP process which allows for quiescent currents which are considerably lower than

those associated with traditional lateral PNP regulators, typically 1500 µA at 250-mA load and 75 µA at 1-mA

load.

7.3.3 Low Noise

The LP2992 includes a low-noise reference ensuring minimal noise during operation because the internal

reference is normally the dominant term in a noise analysis. Further noise reduction can be achieved by adding

an external bypass capacitor between the BYPASS pin and the GND pin. For more detailed information on noise

reduction using the BYPASS pin, see Noise Bypass Capacitor.

7.3.4 Enhanced Stability

The LP2992 is designed specifically to work with ceramic output capacitors using circuitry that allows the

regulator to be stable across the entire range of output current with an output capacitor whose ESR is as low as

5 m

Ω. For output capacitor requirements, see Output Capacitor.

7.3.5 Overcurrent Protection

The internal current-limit circuit is used to protect the LDO against high-current faults or shorting events. The

LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources

constant current. Therefore, the output voltage falls when the output impedance decreases. Note also that if a

current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO,

resulting in a thermal shutdown of the output.

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