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PIC18F2220-I/P Datasheet(PDF) 47 Page - Microchip Technology |
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PIC18F2220-I/P Datasheet(HTML) 47 Page - Microchip Technology |
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47 / 388 page ![]() 2003 Microchip Technology Inc. DS39599C-page 45 PIC18F2220/2320/4220/4320 TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS REGISTER 4-1: RCON REGISTER BITS AND POSITIONS TABLE 4-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Oscillator Configuration Power-up(2) and Brown-out Exit from Power Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) —— RC, RCIO 66 ms(1) —— INTIO1, INTIO2 66 ms(1) —— Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the 4x PLL to lock. R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-1 R/W-1 IPEN — —RI TO PD POR BOR bit 7 bit 0 Note: Refer to Section 5.14 “RCON Register” for bit definitions. Condition Program Counter RCON Register RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 0--1 1100 1 1 1 0 0 0 0 RESET Instruction 0000h 0--0 uuuu 0 u u u u u u Brown-out 0000h 0--1 11u- 1 1 1 u 0 u u MCLR during power managed Run modes 0000h 0--u 1uuu u 1 u u u u u MCLR during power managed Idle modes and Sleep mode 0000h 0--u 10uu u 1 0 u u u u WDT Time-out during full power or power managed Run mode 0000h 0--u 0uuu u 0 u u u u u MCLR during full power execution 0000h 0--u uuuu u u u u u uu Stack Full Reset (STVREN = 1) 1u Stack Underflow Reset (STVREN = 1) u1 Stack Underflow Error (not an actual Reset, STVREN = 0) 0000h u--u uuuu u u u u u u 1 WDT Time-out during power managed Idle or Sleep modes PC + 2 u--u 00uu u 0 0 u u u u Interrupt exit from power managed modes PC + 2 u--u u0uu u u 0 u u u u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). |
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