PIC17C752-08SLASHCL datasheet(252/328 Pages) MICROCHIP

252 / 328 page

PIC17C7XX

DS30289A-page 252

Preliminary

FIGURE 20-9: SPI MASTER MODE TIMING (CKE = 0)

TABLE 20-9:

SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param.

No.

Symbol

Characteristic

Min

Typ† Max Units

Conditions

TssL2scH,

TssL2scL

↓ to SCK↓ or SCK↑ input

TCY *—

—

TscH

SCK input high time

(slave mode)

Continuous 1.25TCY + 30 *

—

71A

Single Byte

—

Note 1

TscL

SCK input low time

(slave mode)

Continuous 1.25TCY + 30 *

—

72A

Single Byte

—

Note 1

TdiV2scH,

TdiV2scL

Setup time of SDI data input to SCK

edge

100 *

—

73A

TB2B

Last clock edge of Byte1 to the 1st clock

edge of Byte2

1.5TCY + 40 *

—

Note 1

TscH2diL,

TscL2diL

Hold time of SDI data input to SCK edge

100 *

—

TdoR

SDO data output rise time

—

25 *

TdoF

SDO data output fall time

—

25 *

TscR

SCK output rise time (master mode)

—

25 *

TscF

SCK output fall time (master mode)

—

25 *

TscH2doV,

TscL2doV

SDO data output valid after SCK edge

—

50 *

Characterized but not tested.

†

Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: Speciﬁcation 73A is only required if speciﬁcations 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

75, 76

MSb

LSb

BIT6 - - - - - -1

MSb IN

LSb IN

BIT6 - - - -1

Refer to Figure 20-1 for load conditions.

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