PIC17C752-08SLASHCL datasheet(283/328 Pages) MICROCHIP

283 / 328 page

DS30289A-page 283

PIC17C7XX

APPENDIX A: MODIFICATIONS

The following is the list of modiﬁcations over the

PIC16CXX microcontroller family:

Instruction word length is increased to 16-bit.

This allows larger page sizes both in program

memory (8 Kwords verses 2 Kwords) and regis-

ter ﬁle (256 bytes versus 128 bytes).

Four modes of operation: microcontroller, pro-

tected microcontroller, extended microcontroller,

and microprocessor.

22 new instructions.

The MOVF, TRIS and OPTION instructions have

been removed.

Four new instructions (TLRD, TLWT, TABLRD,

TABLWT

) for transferring data between data

memory and program memory. They can be

used to “self program” the EPROM program

memory.

Single cycle data memory to data memory

transfers possible (MOVPF and MOVFP instruc-

tions). These instructions do not affect the Work-

ing register (WREG).

W register (WREG) is now directly addressable.

A PC high latch register (PCLATH) is extended

to 8-bits. The PCLATCH register is now both

readable and writable.

Data memory paging is redeﬁned slightly.

DDR registers replaces function of TRIS regis-

ters.

10. Multiple Interrupt vectors added. This can

decrease the latency for servicing interrupts.

11. Stack size is increased to 16 deep.

12. BSR register for data memory paging.

13. Wake up from SLEEP operates slightly differ-

ently.

14. The Oscillator Start-Up Timer (OST) and

Power-Up Timer (PWRT) operate in parallel and

not in series.

15. PORTB interrupt on change feature works on all

eight port pins.

16. TMR0 is 16-bit plus 8-bit prescaler.

17. Second indirect addressing register added

(FSR1 and FSR2). Conﬁguration bits can select

the FSR registers to auto-increment, auto-dec-

rement, remain unchanged after an indirect

address.

18. Hardware multiplier added (8 x 8

→ 16-bit)

19. Peripheral modules operate slightly differently.

20. A/D has both a VREF+ and VREF-.

21. USARTs do not implement BRGH feature.

22. Oscillator modes slightly redeﬁned.

23. Control/Status bits and registers have been

placed in different registers and the control bit

for globally enabling interrupts has inverse

polarity.

24. In-circuit serial programming is implemented dif-

ferently.

APPENDIX B: COMPATIBILITY

convert

code

written

for

PIC16CXXX

PIC17CXXX, the user should take the following steps:

Remove any TRIS and OPTION instructions,

and implement the equivalent code.

Separate the interrupt service routine into its

four vectors.

Replace:

MOVF

REG1, W

with:

MOVFP

REG1, WREG

Replace:

MOVF

REG1, W

MOVWF

REG2

with:

MOVPF

REG1, REG2 ; Addr(REG1)<20h

MOVFP

REG1, REG2 ; Addr(REG2)<20h

Ensure that all bit names and register names are

updated to new data memory map locations.

Verify data memory banking.

Verify mode of operation for indirect addressing.

Verify peripheral routines for compatibility.

Weak pull-ups are enabled on reset.

Upgrading from PIC17C42 Devices

To convert code from the PIC17C42 to all the other

PIC17CXXX devices, the user should take the following

steps.

If the hardware multiply is to be used, ensure

that any variables at address 18h and 19h are

moved to another address.

Ensure that the upper nibble of the BSR was not

written with a non-zero value. This may cause

unexpected operation since the RAM bank is no

longer 0.

The disabling of global interrupts has been

enhanced so there is no additional testing of the

GLINTD bit after a BSF

CPUSTA,

GLINTD

instruction.

Note:

If REG1 and REG2 are both at addresses

greater then 20h, two instructions are

required.

MOVFP

REG1, WREG ;

MOVPF

WREG, REG2 ;

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