PIC17C752-08SLASHCL datasheet(288/328 Pages) MICROCHIP

288 / 328 page

PIC17C7XX

DS30289A-page 288

E.4

Multi-Master

The I2C protocol allows a system to have more than

one master. This is called multi-master. When two or

more masters try to transfer data at the same time, arbi-

tration and synchronization occur.

E.4.1

ARBITRATION

Arbitration takes place on the SDA line, while the SCL

line is high. The master which transmits a high when

the other master transmits a low loses arbitration

(Figure E-9), and turns off its data output stage. A mas-

ter which lost arbitration can generate clock pulses until

the end of the data byte where it lost arbitration. When

the master devices are addressing the same device,

arbitration continues into the data.

FIGURE E-9:

MULTI-MASTER

ARBITRATION

(TWO MASTERS)

Masters that also incorporate the slave function, and

have lost arbitration must immediately switch over to

slave-receiver mode. This is because the winning mas-

ter-transmitter may be addressing it.

Arbitration is not allowed between:

• A repeated START condition

• A STOP condition and a data bit

• A repeated START condition and a STOP condi-

tion

Care needs to be taken to ensure that these conditions

do not occur.

transmitter 1 loses arbitration

DATA 1 SDA

DATA 1

DATA 2

SDA

SCL

E.5

Clock Synchronization

Clock synchronization occurs after the devices have

started

arbitration. This

performed

using

wired-AND connection to the SCL line. A high to low

transition on the SCL line causes the concerned

devices to start counting off their low period. Once a

device clock has gone low, it will hold the SCL line low

until its SCL high state is reached. The low to high tran-

sition of this clock may not change the state of the SCL

line, if another device clock is still within its low period.

The SCL line is held low by the device with the longest

low period. Devices with shorter low periods enter a

high wait-state, until the SCL line comes high. When

the SCL line comes high, all devices start counting off

their high periods. The ﬁrst device to complete its high

period will pull the SCL line low. The SCL line high time

is determined by the device with the shortest high

period, Figure E-10.

FIGURE E-10: CLOCK SYNCHRONIZATION

E.6

I2C Timing Speciﬁcations

Table E-2 (Figure E-11) and Table E-3 (Figure E-12)

show the timing speciﬁcations as required by the Phil-

ips speciﬁcation for I2C. For additional information

please refer to Section 15.2 and Section 20.5.

CLK

SCL

wait

state

start counting

HIGH period

counter

reset

PIC17C752-08/CL Datasheet(PDF) 288 Page - Microchip Technology

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