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PIC17C752-08/CL Datasheet(PDF) 313 Page - Microchip Technology |
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PIC17C752-08/CL Datasheet(HTML) 313 Page - Microchip Technology |
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313 / 328 page  © 1998 Microchip Technology Inc. DS30289A-page 313 PIC17C7XX Restart Condition ...................................................... 155 Start Condition .......................................................... 153 Stop Condition .......................................................... 166 FOSC0 .............................................................................. 189 FOSC1 .............................................................................. 189 FS0 ............................................................................. 49, 292 FS1 ............................................................................. 49, 292 FS2 ............................................................................. 49, 292 FS3 ............................................................................. 49, 292 FSR0 ............................................................................. 46, 53 FSR1 ............................................................................. 46, 53 Fuzzy Logic Dev. System ( fuzzyTECH ®-MP) .................. 233 G GCE .......................................................................... 134, 309 General Call Address Sequence....................................... 147 General Call Address Support .......................................... 147 General Call Enable bit, GCE ................................... 134, 309 General Format for Instructions ........................................ 196 General Purpose RAM ........................................................ 41 General Purpose RAM Bank............................................... 56 General Purpose Register (GPR) ....................................... 44 GLINTD ......................................................... 37, 50, 109, 192 Global Interrupt Disable bit, GLINTD .................................. 37 GOTO ............................................................................... 210 GPR (General Purpose Register) ....................................... 44 GPR Banks ......................................................................... 56 Graphs IOH vs. VOH, VDD = 3V .............................................. 272 IOH vs. VOH, VDD = 5V .............................................. 273 IOL vs. VOL, VDD = 3V ............................................... 273 IOL vs. VOL, VDD = 5V ............................................... 274 Maximum IDD vs. Frequency (External Clock 125 °C to -40°C) ........................................................ 269 Maximum IPD vs. VDD Watchdog Disabled ............... 270 Maximum IPD vs. VDD Watchdog Enabled................ 271 RC Oscillator Frequency vs. VDD (Cext = 100 pF) ... 266 RC Oscillator Frequency vs. VDD (Cext = 22 pF) ..... 266 RC Oscillator Frequency vs. VDD (Cext = 300 pF) ... 267 Transconductance of LF Oscillator vs.VDD ............... 268 Transconductance of XT Oscillator vs. VDD.............. 268 Typical IDD vs. Frequency (External Clock 25 °C) ..... 269 Typical IPD vs. VDD Watchdog Disabled 25 °C .......... 270 Typical IPD vs. VDD Watchdog Enabled 25 °C........... 271 Typical RC Oscillator vs. Temperature ..................... 265 VIH, VIL of MCLR, T0CKI and OSC1 (In RC Mode) vs. VDD...................................................................... 275 VTH (Input Threshold Voltage) of I/O Pins vs. VDD...................................................................... 274 VTH (Input Threshold Voltage) of OSC1 Input (In XT, HS, and LP Modes) vs. VDD......................... 275 WDT Timer Time-Out Period vs. VDD ....................... 272 H Hardware Multiplier ............................................................. 65 I I/O Ports Bi-directional ............................................................... 91 I/O Ports...................................................................... 69 Programming Considerations ..................................... 91 Read-Modify-Write Instructions................................... 91 Successive Operations ............................................... 92 I2C ..................................................................................... 141 Addressing I2C Devices ............................................ 286 Arbitration.................................................................. 288 Combined Format ..................................................... 287 I2C Overview............................................................. 285 Initiating and Terminating Data Transfer................... 285 Master-Receiver Sequence ...................................... 287 Master-Transmitter Sequence .................................. 287 Multi-master.............................................................. 288 START...................................................................... 285 STOP................................................................ 285, 286 Transfer Acknowledge.............................................. 286 I2C Master Mode Receiver Flowchart............................... 161 I2C Master Mode Reception ............................................. 160 I2C Master Mode Restart Condition.................................. 154 I2C Mode Selection........................................................... 141 I2C Module Acknowledge Flowchart............................................ 164 Acknowledge Sequence timing ................................ 163 Addressing................................................................ 143 Baud Rate Generator ............................................... 151 Block Diagram .......................................................... 149 BRG Block Diagram ................................................. 151 BRG Reset due to SDA Collision ............................. 170 BRG Timing .............................................................. 151 Bus Arbitration .......................................................... 168 Bus Collision............................................................. 168 Acknowledge .................................................... 168 Restart Condition.............................................. 171 Restart Condition Timing (Case1) .................... 171 Restart Condition Timing (Case2) .................... 171 Start Condition.................................................. 169 Start Condition Timing .............................. 169, 170 Stop Condition .................................................. 172 Stop Condition Timing (Case1) ........................ 172 Stop Condition Timing (Case2) ........................ 172 Transmit Timing................................................ 168 Bus Collision timing .................................................. 168 Clock Arbitration ....................................................... 167 Clock Arbitration Timing (Master Transmit) .............. 167 Conditions to not give ACK Pulse............................. 142 General Call Address Support.................................. 147 Master Mode............................................................. 149 Master Mode 7-bit Reception timing......................... 162 Master Mode Operation............................................ 150 Master Mode Start Condition.................................... 152 Master Mode Transmission ...................................... 157 Master Mode Transmit Sequence ............................ 150 Master Transmit Flowchart ....................................... 158 Multi-Master Communication.................................... 168 Multi-master Mode.................................................... 150 Operation.................................................................. 141 Repeat Start Condition timing................................... 154 Restart Condition Flowchart ..................................... 155 Slave Mode............................................................... 142 Slave Reception ....................................................... 143 Slave Transmission .................................................. 144 SSPBUF ................................................................... 142 Start Condition Flowchart ......................................... 153 Stop Condition Flowchart ......................................... 166 Stop Condition Receive or Transmit timing .............. 165 Stop Condition timing ............................................... 165 Waveforms for 7-bit Reception ................................. 144 Waveforms for 7-bit Transmission............................ 144 I2C Module Address Register, SSPADD .......................... 142 I2C Slave Mode ................................................................ 142 INCF ................................................................................. 211 INCFSNZ .......................................................................... 212 INCFSZ............................................................................. 211 In-Circuit Serial Programming .......................................... 194 INDF0 ........................................................................... 46, 53 INDF1 ........................................................................... 46, 53 Indirect Addressing Indirect Addressing..................................................... 53 Operation.................................................................... 53 |
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