PIC17C752-08SLASHCL datasheet(192/328 Pages) MICROCHIP

192 / 328 page

PIC17C7XX

DS30289A-page 192

17.4

Power-down Mode (SLEEP)

The Power-down mode is entered by executing a

SLEEP

instruction. This clears the Watchdog Timer and

postscaler (if enabled). The PD bit is cleared and the

TO bit is set (in the CPUSTA register). In SLEEP mode,

the oscillator driver is turned off. The I/O ports maintain

their status (driving high, low, or hi-impedance).

The MCLR/VPP pin must be at a logic high level

(VIHMC). A WDT time-out RESET does not drive the

MCLR/VPP pin low.

17.4.1

WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

• Power-on Reset

• Brown-out Reset

• External reset input on MCLR/VPP pin

• WDT Reset (if WDT was enabled)

• Interrupt from RA0/INT pin, RB port change,

T0CKI interrupt, or some peripheral Interrupts

The following peripheral interrupts can wake the device

from SLEEP:

• Capture interrupts

• USART synchronous slave transmit interrupts

• USART synchronous slave receive interrupts

• A/D conversion complete

• SPI slave transmit / receive complete

•I2C slave receive

Other peripherals cannot generate interrupts since dur-

ing SLEEP, no on-chip Q clocks are present.

Any reset event will cause a device reset. Any interrupt

event is considered a continuation of program execu-

tion. The TO and PD bits in the CPUSTA register can be

used to determine the cause of device reset. The PD

bit, which is set on power-up, is cleared when SLEEP

is invoked. The TO bit is cleared if WDT time-out

occurred (and caused wake-up).

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GLINTD bit. If the GLINTD

bit is set (disabled), the device continues execution at

the instruction after the SLEEP instruction. If the

GLINTD bit is clear (enabled), the device executes the

instruction after the SLEEP instruction and then

branches to the interrupt vector address. In cases

where the execution of the instruction following SLEEP

is not desirable, the user should have a NOP after the

SLEEP

instruction.

The WDT is cleared when the device wakes from

SLEEP, regardless of the source of wake-up.

17.4.1.1

WAKE-UP DELAY

When the oscillator type is conﬁgured in XT or LF

mode, the Oscillator Start-up Timer (OST) is activated

on wake-up. The OST will keep the device in reset for

1024TOSC. This needs to be taken into account when

considering the interrupt response time when coming

out of SLEEP.

Note:

If the global interrupt is disabled (GLINTD

is set), but any interrupt source has both its

interrupt enable bit and the corresponding

interrupt ﬂag bit set, the device will imme-

diately wake-up from sleep. The TO bit is

set, and the PD bit is cleared.

FIGURE 17-3: WAKE-UP FROM SLEEP THROUGH INTERRUPT

OSC1

CLKOUT(4)

INT

INTF ﬂag

GLINTD bit

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

Interrupt Latency (2)

PC+1

PC+2

0004h

0005h

Dummy Cycle

Inst (PC) = SLEEP

Inst (PC+1)

Inst (PC-1)

SLEEP

Tost(2)

Processor

in SLEEP

Inst (PC+2)

Inst (PC+1)

Note 1: XT or LF oscillator mode assumed.

2: Tost = 1024Tosc (drawing not to scale). This delay will not be there for RC osc mode.

3: When GLINTD = 0 processor jumps to interrupt routine after wake-up. If GLINTD = 1, execution will continue in line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

(RA0/INT pin)

'0' or '1'

PIC17C752-08/CL Datasheet(PDF) 192 Page - Microchip Technology

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