PIC18C658T-ESLASHCL datasheet(161/366 Pages) MICROCHIP

161 / 366 page

 2000 Microchip Technology Inc.

Advanced Information

DS30475A-page 161

PIC18CXX8

15.4.12 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated START/STOP condition,

de-asserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the baud rate

generator (BRG) is suspended from counting until the

SCL pin is actually sampled high. When the SCL pin is

sampled high, the baud rate generator is reloaded with

the contents of SSPADD<6:0> and begins counting.

This ensures that the SCL high time will always be at

least one BRG rollover count, in the event that the clock

is held low by an external device (Figure 15-19).

15.4.13 SLEEP OPERATION

While in SLEEP mode, the I2C module can receive

addresses or data, and when an address match or

complete byte transfer occurs, wake the processor

from SLEEP (if the MSSP interrupt is enabled).

15.4.14 EFFECT OF A RESET

A RESET disables the MSSP module and terminates

the current transfer.

FIGURE 15-19: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE

SCL

SDA

BRG overflow,

Release SCL,

If SCL = 1 Load BRG with

SSPADD<6:0>, and start count

BRG overflow occurs,

Release SCL, Slave device holds SCL low.

SCL = 1 BRG starts counting

clock high interval.

SCL line sampled once every machine cycle (TOSC² 4).

Hold off BRG until SCL is sampled high.

TBRG

to measure high time interval.

PIC18C658T-E/CL Datasheet(PDF) 161 Page - Microchip Technology