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PIC18C242-I/P Datasheet(PDF) 26 Page - Microchip Technology |
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PIC18C242-I/P Datasheet(HTML) 26 Page - Microchip Technology |
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26 / 296 page  PIC18CXX2 DS39026B-page 26 Preliminary © 7/99 Microchip Technology Inc. TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Reset Instruction Stack Resets Wake-up via WDT or Interrupt TOSU 242 442 252 452 ---0 0000 ---0 0000 ---0 uuuu (3) TOSH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu (3) TOSL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu (3) STKPTR 242 442 252 452 00-0 0000 00-0 0000 uu-u uuuu (3) PCLATU 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu PCLATH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu PCL 242 442 252 452 0000 0000 0000 0000 PC + 2 (2) TBLPTRU 242 442 252 452 --00 0000 --00 0000 --uu uuuu TBLPTRH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu TBLPTRL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu TABLAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu PRODH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 242 442 252 452 0000 000x 0000 000u uuuu uuuu (1) INTCON2 242 442 252 452 1111 -1-1 1111 -1-1 uuuu -u-u (1) INTCON3 242 442 252 452 11-0 0-00 11-0 0-00 uu-u u-uu (1) INDF0 242 442 252 452 N/A N/A N/A POSTINC0 242 442 252 452 N/A N/A N/A POSTDEC0 242 442 252 452 N/A N/A N/A PREINC0 242 442 252 452 N/A N/A N/A PLUSW0 242 442 252 452 N/A N/A N/A FSR0H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu FSR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu WREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 242 442 252 452 N/A N/A N/A POSTINC1 242 442 252 452 N/A N/A N/A POSTDEC1 242 442 252 452 N/A N/A N/A PREINC1 242 442 252 452 N/A N/A N/A PLUSW1 242 442 252 452 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard- ware stack. 4: See Table 3-2 for reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR reset. 7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’. |
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