PIC16C54-04SLASHSS datasheet(35/84 Pages) MICROCHIP

35 / 84 page

Preliminary

DS40191A-page 35

PIC16CR54C

7.9

Power-Down Mode (SLEEP)

A device may be powered down (SLEEP) and later

powered up (Wake-up from SLEEP).

7.9.1

SLEEP

The Power-Down mode is entered by executing a

SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low, or hi-impedance).

It should be noted that a RESET generated by a WDT

time-out does not drive the MCLR/VPP pin low.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

MCLR/VPP pin must be at a logic high level

(VIH MCLR).

7.9.2

WAKE-UP FROM SLEEP

The device can wake up from SLEEP through one of

the following events:

An external reset input on MCLR/VPP pin.

A Watchdog Timer time-out reset (if WDT was

enabled).

Both of these events cause a device reset. The TO and

PD bits can be used to determine the cause of device

reset.

The TO bit is cleared if a WDT time-out

occurred (and caused wake-up). The PD bit, which is

set on power-up, is cleared when SLEEP is invoked.

The WDT is cleared when the device wakes from

sleep, regardless of the wake-up source.

7.10

Program Veriﬁcation/Code Protection

the

code

protection

bit(s)

have

not

been

programmed, the on-chip program memory can be

read out for veriﬁcation purposes.

Note:

Microchip does not recommend code pro-

tecting windowed devices.

PIC16C54-04/SS Datasheet(PDF) 35 Page - Microchip Technology

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