W97AH6KB datasheet(21/127 Pages) WINBOND

21 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 21 -

7.3.3.1

Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC)

Burst Cycle Number and Burst Address Sequence

wrap

any

y+1 y+2 y+3

wrap

seq

int

any

illegal (not allowed)

wrap

seq

int

illegal (not allowed)

any

illegal (not allowed)

Notes:

1. C0 input is not present on CA bus. It is implied zero.

2. For BL=4, the burst address represents C[1: 0].

3. For BL=8, the burst address represents C[2:0].

4. For BL=16, the burst address represents C[3:0].

5. For no-wrap (nw), BL4, the burst shall not cross the page boundary and shall not cross sub-page boundary. The variable y may start at

any address with C0 equal to 0 and may not start at any address shown in table below.

7.3.3.2

Non Wrap Restrictions

Bus Width

1Gb

Not across full page boundary

x16

3FE, 3FF, 000, 001

x32

1FE, 1FF, 000, 001

Not across sub page boundary

x16

1FE, 1FF, 200, 201

x32

None

Note: Non-wrap BL=4 data-orders shown above are prohibited.

W97AH6KB Datasheet(PDF) 21 Page - Winbond

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