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LM2694MT/NOPB Datasheet(PDF) 16 Page - Texas Instruments |
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LM2694MT/NOPB Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 26 page ![]() LM2694 SNVS444A – MAY 2006 – REVISED APRIL 2013 www.ti.com PC BOARD LAYOUT and THERMAL CONSIDERATIONS The LM2694 regulation, over-voltage, and current limit comparators are very fast, and will respond to short duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be as neat and compact as possible, and all the components must be as close as possible to their associated pins. The two major current loops have currents which switch very fast, and so the loops should be as small as possible to minimize conducted and radiated EMI. The first loop is that formed by C1, through the VIN to SW pins, L1, C2, and back to C1. The second loop is that formed by D1, L1, C2, and the SGND and ISEN pins. The ground connection from C2 to C1 should be as short and direct as possible, preferably without going through vias. Directly connect the SGND and RTN pin to each other, and they should be connected as directly as possible to the C1/C2 ground line without going through vias. The power dissipation within the IC can be approximated by determining the total conversion loss (PIN - POUT), and then subtracting the power losses in the free-wheeling diode and the inductor. The power loss in the diode is approximately: PD1 = IO x VF x (1-D) where • Io is the load current • VF is the diode’s forward voltage drop • D is the duty cycle (23) The power loss in the inductor is approximately: PL1 = IO 2 x R L x 1.1 where • RL is the inductor’s DC resistance • 1.1 factor is an approximation for the AC losses (24) If it is expected that the internal dissipation of the LM2694 will produce high junction temperatures during normal operation, good use of the PC board’s ground plane can help considerably to dissipate heat. The exposed pad on the WSON package bottom should be soldered to a ground plane, and that plane should both extend from beneath the IC, and be connected to exposed ground plane on the board’s other side using as many vias as possible. The exposed pad is internally connected to the IC substrate. The use of wide PC board traces at the pins, where possible, can help conduct heat away from the IC. The four No Connect pins on the TSSOP package are not electrically connected to any part of the IC, and may be connected to ground plane to help dissipate heat from the package. Judicious positioning of the PC board within the end product, along with the use of any available air flow (forced or natural convection) can help reduce the junction temperature. 16 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM2694 |
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