ML6510 datasheet(13/18 Pages) MICRO-LINEAR

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ML6510

TABLE 2: ML6510-130 ROM CODES

SELECTION BITS

INPUT OUTPUT

CONFIGURATION CODE

FREQ

CODE DESCRIPTION

ROMMSB

MCLK MDOUT (MHz) (MHz)

CM R1, R0

DDSK

TEST

PECL Input Clock, 1x mode

80-130 80-130

PECL Input Clock, 0.5x mode

80-160

40-80

PECL Input Clock, 2x mode

40-65

80-130

PECL Input Clock, 1x mode

80-130 80-130

TTL Input Clock, 1x mode

80-130 80-130

TTL Input Clock, 0.5x mode

80-130

40-65

TTL Input Clock, 2x mode

40-65

80-130

TEST mode, TTL Input clock

0-50

—

TABLE 1: ML6510-80 ROM CODES

SELECTION BITS

INPUT

OUTPUT

CONFIGURATION CODE

FREQ

CODE DESCRIPTION

ROMMSB

MCLK MDOUT

(MHz)

CM R1, R0

TEST

PECL Input Clock, 1x mode

40-80

PECL Input Clock, 0.5x mode

40-80

20-40

PECL Input Clock, 2x mode

20-40

40-80

PECL Input Clock, 1x mode

40-80

TTL Input Clock, 1x mode

40-80

TTL Input Clock, 0.5x mode

40-80

20-40

TTL Input Clock, 2x mode

20-40

40-80

TEST mode, TTL Input clock

0-50

—

Figure 6. AUX Mode Waveform.

MCLK

(Input to ML6510)

MDOUT

(Input to ML6510)

tA1

tA2

tA5

tA3

tA4

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