7

Figure 7. The ML65245 in a non-cache, main memory RISC application. The main memory could be DRAM or

Cache DRAM. The ML65245 can be used as a data I/O transceiver as well as an address buffer, as shown above.

66 MHz

Pentium™ Processor

CACHE

(SRAM)

ML65245 BUFFER

CONTROL

ADDRESS

PCMC

LATCH

CONTROL

ADDRESS/DATA

WE

MAddr

LBX

BMAddr

BWE

DATA

LBX CNTL

PCI™ BUS (33 MHz)

MAIN MEMORY

(DRAM)

CNTL

DATA

LOCAL BUS

R4X00™

150/75 MHz

CDRAM

or

DRAM

CDRAM

or

DRAM

MEMORY I/O

CONTROLLER

ML65245

CONTROL

ADDR

CONTROL

ADDRESS/DATA

ML65245

ML65245

Figure 6. ML65245 in a main memory application for a Pentium based system. The high drive and low propagation

delay are essential to buffer the write enable and memory addresses to the main memory SIIMMs.