LM5027A

SNVS642B – APRIL 2010 – REVISED MARCH 2013

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DETAILED OPERATING DESCRIPTION

The LM5027A PWM controller contains all the features necessary to implement power converters utilizing the

Active Clamp Reset technique with synchronous rectification. The device is configured to control a P-Channel

clamp switch. With the active clamp technique higher efficiencies and greater power densities can be realized

compared to conventional catch winding or RDC clamp / reset techniques. The LM5027A provides three gate

driver outputs: one to drive the primary side MOSFET (OUTA), one for the active clamp P-Channel MOSFET

(OUTB), and one output to drive the synchronous rectifier through an isolation interface (OUTSR). This controller

is designed for high-speed operation including an oscillator frequency range up to 1 MHz and total PWM and

current sense propagation delay less than 50 ns. The LM5027A includes a high-voltage start-up regulator that

operates over a wide input range of 13V to 90V. Additional features include: Line Under-Voltage lockout (UVLO),

soft-start/soft-stop, oscillator with synchronization capability, cycle-by-cycle current limit, hiccup mode fault

protection with adjustable delay, precision reference, and thermal shutdown.

High Voltage Start-Up Regulator

The LM5027A contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected

directly to the line voltage. The regulator output is internally current limited to 55mA. When the UVLO pin

potential is greater than 0.4V, the VCC regulator is enabled to charge an external capacitor connected to the

VCC pin. The VCC regulator provides power to the voltage reference (REF) and the gate drivers (OUTA, OUTB,

and OUTSR). The controller outputs are enabled when the voltage on the VCC pin reaches the regulation point

of 9.5V, the internal voltage reference (REF) reaches its regulation point of 5V, the UVLO pin voltage is greater

than 2V, and the OTP pin voltage is greater than 1.25V. The outputs will remain enabled unless one of the

following conditions occurs, VCC falls below 6.0V, UVLO is below 2.0 V, or the OTP pin falls below 1.25V. The

value selected for the VCC capacitor depends on the total system design and the start-up characteristics. The

recommended capacitance range for the VCC regulator is 0.1 µF to 100 µF. In a typical application, an auxiliary

transformer winding is connected through a diode to the VCC pin. This winding must raise the VCC voltage

above the VCC regulation set point to shut off the internal start-up regulator. The LM5027A lowers the VCC

regulation set point from 9.5V to 7.5V after the output of the first OUTSR drive pulse. Powering VCC from an

auxiliary winding improves efficiency while reducing the controller power dissipation. When the converter auxiliary

winding is inactive, external current draw on the VCC line should be limited so the power dissipation in the start-

up regulator does not exceed the maximum power dissipation of the LM5027A package. An external start-up

regulator or other bias rail can be used instead of the internal start-up regulator by connecting the VCC and the

VIN pins together and feeding the external bias into the two pins.

Line Under-Voltage Detector

The LM5027A contains a dual level line Under Voltage Lock Out (UVLO) circuit. When the UVLO pin voltage is

greater than 0.4V but less than 2.0V, the controller is in a standby mode. In the standby mode the VCC and REF

bias regulators are active while the controller outputs are disabled. This feature allows the UVLO pin to be used

as a remote enable/disable function. Pulling the UVLO pin below the 2.0V threshold initiates a soft-stop

sequence described later in this document. There is 100mV of hysteresis provided in the 0.4V shutdown

comparator. When the VCC and REF outputs exceed their respective under-voltage thresholds and the UVLO

pin voltage is greater than 2.0V and the OTP pin voltage is greater than 1.25V, the outputs are enabled and

normal operation begins. An external set-point voltage divider from the VIN to GND can be used to set the

minimum operating voltage of the converter. The divider must be designed such that the voltage at the UVLO pin

will be greater than 2.0V when Vin is in the desired operating range. If the under-voltage threshold is not met, all

three outputs are disabled. UVLO hysteresis is accomplished with an internal 20 µA current sink that is switched

on or off into the impedance of the set-point divider. When the UVLO pin voltage exceeds 2.0V threshold, the

current sink is deactivated to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below

the 2.0V threshold, the current sink is turned on causing the voltage at the UVLO pin to quickly fall .

Reference

The REF pin is the output of a 5V linear regulator that can be used to bias an opto-coupler transistor and

external house-keeping circuits. The regulator output is internally current limited to 10 mA.

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