A43L0616B datasheet(2/48 Pages) AMICC

2 / 48 page

A43L0616B

512K X 16 Bit X 2 Banks Synchronous DRAM

(February, 2008, Version 1.3)

AMIC Technology, Corp.

Features

JEDEC standard 3.3V power supply

LVTTL compatible with multiplexed address

Dual banks / Pulse RAS

MRS cycle with address key programs

- CAS Latency (2,3)

- Burst Length (1,2,4,8 & full page)

- Burst Type (Sequential & Interleave)

All inputs are sampled at the positive going edge of the

system clock

Industrial operating temperature range: -40ºC to +85ºC

for –U

Pb-Free type for -F

Burst Read Single-bit Write operation

DQM for masking

Auto & self refresh

32ms refresh period (2K cycle)

Available in 54 Balls CSP (8mm X 8mm) and 50-pin

TSOP(II) packages

All Pb-free (Lead-free) products are RoHS compliant

General Description

The A43L0616B is 16,777,216 bits synchronous high data

rate Dynamic RAM organized as 2 X 524,288 words by 16

bits, fabricated with AMIC’s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock. I/O transactions are possible on

every

clock

cycle.

Range

operating

frequencies,

programmable latencies allows the same device to be useful

for a variety of high bandwidth, high performance memory

system applications.

Pin Configuration

54 Balls CSP (8 mm x 8 mm)

Top View

54 Ball (6X9) CSP

VSS

DQ15

VSSQ

VDDQ

DQ0

VDD

DQ14

DQ13

VDDQ

VSSQ

DQ2

DQ1

DQ12

DQ11

VSSQ

VDDQ

DQ4

DQ3

DQ10

DQ9

VDDQ

VSSQ

DQ6

DQ5

DQ8

VSS

VDD

LDQM

DQ7

UDQM

CLK

CKE

CAS

RAS

A10

VSS

VDD

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