LX1664/64A, LX1665/65A

PRODUCT DA T ABOOK 1996/1997

Copyright © 1999

Rev. 1.2 11/99

16

LAYOUT GUIDELINES - THERMAL DESIGN

A great deal of time and effort were spent optimizing the thermal

design of the demo boards. Any user who intends to implement

an embedded motherboard would be well advised to carefully

read and follow these guidelines. If the FET switches have been

carefully selected, external heatsinking is generally not required.

However, this means that copper trace on the PC board must now

be used. This is a potential trouble spot; as much copper area as

possible must be dedicated to heatsinking the FET switches, and

the diode as well if a non-synchronous solution is used.

In our VRM module, heatsink area was taken from internal

ground and V

with VIAS to the power device tabs. The TO-220 and TO-263

cases are well suited for this application, and are the preferred

packages. Remember to remove any conformal coating from all

exposed PC traces which are involved in heatsinking.

General Notes

As always, be sure to provide local capacitive decoupling close to

the chip. Be sure use ground plane construction for all high-

frequency work. Use low ESR capacitors where justified, but be

alert for damping and ringing problems. High-frequency designs

demand careful routing and layout, and may require several

iterations to achieve desired performance levels.

Power Traces

To reduce power losses due to ohmic resistance, careful consid-

eration should be given to the layout of traces that carry high

currents. The main paths to consider are:

I Input power from 5V supply to drain of top MOSFET.

I Trace between top MOSFET and lower MOSFET or Schottky

diode.

I Trace between lower MOSFET or Schottky diode and

ground.

I Trace between source of top MOSFET and inductor, sense

resistor and load.

FIGURE 15 — Power Traces

Output

Input

5V or 12V

LX166x

3.3

12

10

3.30

3.2

11.3

10

3.20

3.1

11.3

10.7

3.08

3.0

11

11

3.00

2.9

10.3

11

2.90

2.8

10

11.5

2.80

2.7

10

12.4

2.71

2.6

10

13.7

2.59

2.5

9.76

14.7

2.50

2.4

8.87

14.7

2.41

2.3

8.87

16.5

2.31

2.2

8.87

18.7

2.21

2.1

8.87

22.1

2.10

2.0

8.87

26.7

2.00

1.9

8.87

21

2.13

1.8

7.15

35.7

1.80

1.7

7.15

53.6

1.70

1.6

7.15

100

1.61

1.5

7.15

∞

1.50

Nominal

Set Point (V)

R

Ω

Ω

Ω

Ω)R

Ω

Ω

Ω

Ω)V

TABLE 6 -

Resistors Settings for Linear Regulator Output Voltage

USING THE LX1664/65 DEVICES

Capacitor Selection

Referring to the Product Highlight schematic on the front page, the

standard value to use as the linear regulator stage output capacitor

is on the order of 330µF. This provides sufficient hold-up for all

expected transient load events in memory and I/O circuitry.

Disabling Linear Output

Linear regulator output can be disabled by pulling feedback pin

(L

FIGURE 14 — Enabling Linear Regulator

L

DRV

LX1664

10

9

L

FB

Supply Voltage

For I/O Chipset

Q

4

IRLZ44

R

5

R

6

C

7

330µF

C

9

330µF

LIN EN

10k

5V

C

10

0.1µF

10k

2N2222

LIN EN

LIN OUTPUT

H

Disabled

L

Enabled

TABLE 7 - Linear Enable (LIN EN) Function Table