SG1842/SG1843 Series

PRODUCT DA T ABOOK 1996/1997

13

Copyright © 2000

Rev. 1.6

4/00

TYPICAL APPLICA TION CIRCUITS

(continued)

FIGURE 23. — SLOPE COMPENSATION

High-peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be

connected to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply

an adjustable ramp to pin 3.

Due to inherent instability of current mode converters running above 50% duty cycle, a slope compensation should be added to

either current sense pin or the error amplifier. Figure 23 shows a typical slope compensation technique.

OSCILLATOR

V

REF

GOOD LOGIC

S

R

5V

REF

INTERNAL

BIAS

8(14)

4(7)

2(3)

1(1)

R

F

C

F

R

d

R

i

From V

O

R

SLOPE

2N222A

R

T

5V

UVLO

2.5V

ERROR

AMP

C

T

1V

2R

R

C.S.

COMP

PWM

LATCH

5(9)

3(5)

5(8)

CR

S

R

6(10)

7(11)

7(12)

V

CC

V

O

Q1

SG1842/43

V

IN

5V

FIGURE 24. — OPEN LOOP LABORATORY FIXTURE

2

3

4

8

7

6

5

COMP

V

FB

I

SENSE

R

V

REF

V

CC

OUTPUT

GROUND

0.1µF

0.1µF

A

SG1842/43

R

T

2N2222

100K

4.7K

1K

4.7K

5K

I

SENSE

ADJUST

ERROR AMP

ADJUST

C

T

1K

GROUND

OUTPUT

V

CC

V

REF

1