M37274MA-082SP datasheet(47/131 Pages) MITSUBISHI

47 / 131 page

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

M37274MA-XXXSP

PRELIMINARY

Notice:

This

is not

a final

specification.

Some

paramentic

limits

are

subject

to change.

s Bit 3: Arbitration LostV Detecting Flag (AL)

In the master transmission mode, when a device other than the mi-

crocomputer sets the SDA to “L,”, arbitration is judged to have been

lost, so that this bit is set to “1.” At the same time, the TRX bit is set to

“0,” so that immediately after transmission of the byte whose arbitra-

tion was lost is completed, the MST bit is set to “0.” When arbitration

is lost during slave address transmission, the TRX bit is set to “0”

and the reception mode is set. Consequently, it becomes possible to

receive and recognize its own slave address transmitted by another

master device.

VArbitration lost: The status in which communication as a master is

disabled.

s Bit 4: I2C-BUS Interface Interrupt Request Bit (PIN)

This bit generates an interrupt request signal. Each time 1-byte data

is transmitted, the state of the PIN bit changes from “1” to “0.” At the

same time, an interrupt request signal is sent to the CPU. The PIN bit

is set to “0” in synchronization with a falling edge of the last clock

(including the ACK clock) of an internal clock and an interrupt re-

quest signal occurs in synchronization with a falling edge of the PIN

bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock

generation is disabled. Figure 40 shows an interrupt request signal

generating timing chart.

The PIN bit is set to “1” in any one of the following conditions.

• Executing a write instruction to the I2C data shift register (address

00F616).

• When the ESO bit is “0”

• At reset

The conditions in which the PIN bit is set to “0” are shown below:

• Immediately after completion of 1-byte data transmission (includ-

ing when arbitration lost is detected)

• Immediately after completion of 1-byte data reception

• In the slave reception mode, with ALS = “0” and immediately after

completion of slave address or general call address reception

• In the slave reception mode, with ALS = “1” and immediately after

completion of address data reception

s Bit 5: Bus Busy Flag (BB)

This bit indicates the status of use of the bus system. When this bit is

set to “0,” this bus system is not busy and a START condition can be

generated. When this bit is set to “1,” this bus system is busy and the

occurrence of a START condition is disabled by the START condi-

tion duplication prevention function (Note).

This flag can be written by software only in the master transmission

mode. In the other modes, this bit is set to “1” by detecting a START

condition and set to “0” by detecting a STOP condition. When the

ESO bit of the I2C control register (address 00F916) is “0” and at

reset, the BB flag is kept in the “0” state.

s Bit 6: Communication Mode Specification Bit (transfer direction

specification bit: TRX)

This bit decides the direction of transfer for data communication. When

this bit is “0,” the reception mode is selected and the data of a trans-

mitting device is received. When the bit is “1,” the transmission mode

is selected and address data and control data are output into the

SDA in synchronization with the clock generated on the SCL.

When the ALS bit of the I2C control register (address 00F916) is “0”

in the slave reception mode is selected, the TRX bit is set to “1”

(transmit) if the least significant bit (R/W bit) of the address data trans-

mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is

“0,” the TRX bit is cleared to “0” (receive).

The TRX bit is cleared to “0” in one of the following conditions.

• When arbitration lost is detected.

• When a STOP condition is detected.

• When occurence of a START condition is disabled by the START

condition duplication prevention function (Note).

• With MST = “0” and when a START condition is detected.

• With MST = “0” and when ACK non-return is detected.

• At reset

s Bit 7: Communication Mode Specification Bit (master/slave speci-

fication bit: MST)

This bit is used for master/slave specification for data communica-

tion. When this bit is “0,” the slave is specified, so that a START

condition and a STOP condition generated by the master are re-

ceived, and data communication is performed in synchronization with

the clock generated by the master. When this bit is “1,” the master is

specified and a START condition and a STOP condition are gener-

ated, and also the clocks required for data communication are gen-

erated on the SCL.

The MST bit is cleared to “0” in one of the following conditions.

• Immediately after completion of 1-byte data transmission when ar-

bitration lost is detected

• When a STOP condition is detected.

• When occurence of a START condition is disabled by the START

condition duplication preventing function (Note).

• At reset

Note: The START condition duplication prevention function disables

the START condition generation, reset of bit counter reset,

and SCL output, when the following condition is satisfied:

• a START condition is set by another master device.

M37274MA-082SP Datasheet(PDF) 47 Page - Mitsubishi Electric Semiconductor

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