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ACE9050 Datasheet(PDF) 7 Page - Mitel Networks Corporation |
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ACE9050 Datasheet(HTML) 7 Page - Mitel Networks Corporation |
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7 / 52 page  ACE9050 7 Description Symbol Units Turbo clock Typ. Max. Min. Normal clock Typ. Max. Min. tECLK tADVCSL tCSLCLL tOELCLL tDAVCLL tCLLDAI tCLLOEH tCLLCSH tCLLADI Cycle time Address valid to CS low Chip Select set-up time OEN set-up time Data set-up time Data hold time OEN hold time CS hold time Address hold time ns ns ns ns ns ns ns ns ns 2 445 240 35 0 0 9 7 496 4 480 245 1 24 18 9 490 248 4 45 42 2 940 485 35 0 0 9 7 992 4 972 492 1 24 18 9 985 495 4 45 42 Timing Cycle Conditions Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 185°C, VDD = 13·6V to 15·5V Typical timings: TAMB = 125°C, VDD = 13·75V Table 3 ACE9050 6303 Read cycle timing NORMAL MODE PROCESSOR INTERFACE Read Cycle tADVCSL tECLK tCSLCLL tOELCLL tDAVCLL ECLK ADDR CS OEN DATA tCLLADI tCLLCSH tCLLDAI tCLLOEH Fig.4 ACE9050 6303 Read cycle timing diagram TIMING DIAGRAMS |
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