GP2021 datasheet(31/62 Pages) MITEL

31 / 62 page

GP2021

CHx_EPOCH_CHECK

(Read Address)

Bits 15 to 14: Not used.

Bits 13 to 8 : Instantaneous value of CHx_20MS_EPOCH.

Bits 7 to 5 : Not used.

Bits 4 to 0 : Instantaneous value of CHx_1MS_EPOCH.

Reading this address gives the instantaneous value of the

CHx_1MS_EPOCH and the CHx_20MS_EPOCH counters. It

can be used to verify if the Epoch counters have been properly

initialised by the software. Its value is not latched and is

incremented on each DUMP. To ensure the correct result, this

getting a DUMP during the read cycle, by synchronising the

read to NEW_ACCUM_DATA. The ranges of these values are

the same as those seen in the CHx_EPOCH register.

CHx_EPOCH

(Read Address)

Bits 15, 14, 7, 6 and 5: Not used. Read gives Low.

Bits 13 to 8: CHx_20MS_EPOCH: The 20 ms epoch counter

value that was sampled at the last TIC event, with a valid range

from 0 to 49.

Bits 4 to 0: CHx_1MS_EPOCH: The 1 ms epoch counter value

that was sampled at the last TIC event, with a valid range from

0 to 19.

CHx_EPOCH_COUNT_LOAD

MULTI_EPOCH_COUNT_LOAD

ALL_EPOCH_COUNT_LOAD

(Write Address)

Bits 15, 14, 7, 6, and 5: Not used.

Bits 13 to 8: CHx_20MS_EPOCH: The value to be loaded into

the 20 millisecond epoch counter, with a valid range from 0 to

49.

Bits 4 to 0: CHx_1MS_EPOCH: The value to be loaded into the

1 millisecond epoch counter, with a valid range from 0 to 19.

This operation is affected by the current channel mode,

(PRESET or UPDATE). In UPDATE mode, the data written

into these registers is immediately transferred to the 1 ms and

20 ms epoch counters. In PRESET mode however, the data

is transferred only after the next TIC. It is important to load the

CHx_EPOCH register last in the PRESET mode loading

sequence because the trailing edge of a write to this register

enables the whole PRESET operation on the next TIC. Refer

to Detailed Operation of the GP2021 for more details of the

PRESET mode. *

* Refer to page 23

half chips in a GPS C/A code, a programmed value of 2047 is

equivalent to a programmed value of 1, but the next DUMP

event will take place 1 ms later. In PRESET mode, the slew

timing is set only by TIC, which will also reset the code

generator, (no DUMP is needed). A non–zero slew must

always be programmed when using PRESET mode.

The CHx_CODE_SLEW register can be written to at any time.

If two accesses have taken place before a DUMP in UPDATE

mode or before a TIC when in PRESET mode, the latest value

will be used at the next slew operation. During the time a slew

process is being executed, any further write access to the

CHx_CODE_SLEW register will be stored until the following

DUMP and then cause the transfer of this new value into the

counter. This situation may be avoided by synchronising the

access with the associated CHx_NEW_ACCUM_DATA

status bit.

If a channel is inactive, a non–zero slew value should be

written into CHx_CODE_SLEW before the channel is

released. This write will be acted on immediately the reset is

released.

If a TIC occurs during or soon after a slew the channel will

not be locked to the satellite, so the Measurement Data for that

channel will not be of use.

The ability to read the Slew counter is included only for

testing hardware or software and has no other use. It will only

give a non–zero result if the read occurs during the actual slew

operation. An example of a slewing event is shown in Fig.23.

t1: Load 5 into CHx_CODE_SLEW register = 2.5 chips delay

1023 CHIPS

1025.5 CHIPS

DUMP

TIME

C/A CODE CHIP NO.:

1021

1022

1023

Fig.23 Slew timing in UPDATE mode

GP2021 Datasheet(PDF) 31 Page - Mitel Networks Corporation

GP2021 Datasheet(HTML) 31 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL