MH89760BS datasheet(22/38 Pages) MITEL

22 / 38 page

4-76

MH89760B

Preliminary Information

The switch matrix can be built so that the maximum

throughput delay is 1 frame +2 channels. The switch

matrix will not only route data channels to their

destination, but it will also route the received

signalling bits through to the destination channel.

This is necessary because the receiving MH89760B

decodes

the

stream,

and

the

transmitting

MH89760B has to reconstruct the outgoing T1

stream. In other words, there is no multiframe

integrity between received data and transmitted

data. The total throughput delay is one frame plus

ten ST-BUS channels for the MH89760B receiver,

2.5 ST-BUS channels for the MH89760B transmitter,

and one frame plus two ST-BUS channels for the

switch matrix for a total of 2.5 frames worst case.

The control block only interfaces with the switch

matrix. Besides routing channels and signalling

through to the proper destination, the switch matrix

must also supply the Master Control Words, and

monitor

the

Master

Status

Words

for

each

MH89760B.

The clock generation block supplies the ST-BUS

clocks

and

the

transmit

clocks

that

are

synchronized to one of the T1 trunks. All of the

extracted 8 kHz outputs are NANDed together before

they are input to PLL #2 of the MT8941.

Phase-locked Loop #2 of the MT8941, will generate

ST-BUS clock signals for the MH89760Bs and the

MT8980s that are synchronized with the chosen T1

line. The E8Ko of all of the other MH89760Bs can be

tristated from the Master Control Word, which allows

the system controller to select any one of 128 T1

lines to act as the synchronization source. By

Figure 15 - Digital Access Cross Connect System (DACS)

Switch

Matrix

Control

Matrix

MT8980

MT8941

MH89760B

T1 Interfaces

Clock

Generator

izer

Equal-

izer

DSTi

DSTo

CSTi0

CSTo

CSTi1

C2i

F0i

C1.5i

OUTA

OUTB

RxT

RxR

E8Ko

DSTi

DSTo

CSTi0

CSTo

CSTi1

C2i

F0i

C1.5i

OUTA

OUTB

RxT

RxR

E8Ko

STi7

STo7

STi0

STo0

F0i

C4i

F0i

C4i

STi7

STo7

STi0

STo0

STo1

STo2

F0i

C4i

C2i

C1.5i

CVb

F0i

F0b

C4b

C20

DPLL #2

C12i

C16i

C8Kb

12.352

MHz Osc.

16.384

•

Equal-

DPLL #1

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