MT88E45 datasheet(10/27 Pages) MITEL

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MT88E45

Advance Information

FSK Data Interface

The MT88E45 provides a powerful dual mode 3-wire

interface so that the data bytes in the demodulated

FSK bit stream can be extracted without the need

either for an external UART or for the CPE’s

microcontroller to perform the function in software.

The interface is speciﬁcally designed for the 1200

baud rate and is consisted of 3 pins: DATA, DCLK

(Data Clock) and DR (Data Ready). DR/STD is a

dual purpose output pin. When FSK is selected it is

DR.

Two modes (modes 0 and 1) are selectable via the

CB0 pin. In mode 0, the FSK bit stream is output

directly. In mode 1, the data byte and the trailing stop

bit are stored in a 9 bit buffer. If mode 1 is desired,

the CB0 pin can be hardwired to Vdd. If mode 0 is

desired and full chip power down is not required, the

CB0 pin can be hardwired to Vss.

In Bellcore’s off-hook protocol, a Type 2 CPE should

restore the voicepath within 50ms after the end of

the FSK signal. Due to noise, end of carrier detection

is not always reliable. The draft TIA Type 2 standard

has proposed that the CPE must detect the end of

FSK when any one of the following occurs:

•

absence of carrier signal or,

•

more than ﬁve framing errors (trailing stop bit a

0 instead of a 1) have been detected in the FSK

message or,

•

more than 150ms of continuous mark signal or

space signal has been detected.

Mode 0 - Bit Stream Mode

This mode is selected when the CB0 pin is low. In

this mode the FSK data is output directly to the DATA

pin. DCLK and DR pins are timing signal outputs

(see Figure 13).

For each received stop and start bit sequence, the

MT88E45 outputs a ﬁxed frequency clock string of 8

pulses at the DCLK pin. Each DCLK rising edge

occurs in the middle of a DATA bit cell. DCLK is not

generated for the start and stop bits. Consequently,

DCLK will clock only valid data into a peripheral

device such as a serial to parallel shift register or a

microcontroller. The MT88E45 also outputs an end

of word pulse (Data Ready) at the DR pin. DR goes

low for half a nominal bit time at the beginning of the

trailing stop bit. It can be used to interrupt a

microcontroller or cause a serial to parallel converter

to parallel load its data into the microcontroller. Since

the DR rising edge occurs in the middle of the stop

bit, it can also be used to read the stop bit to check

for framing error.

Alternatively, DCLK and DATA may occupy 2 bits of a

microcontroller’s input port. The microcontroller polls

the input port and saves the DATA bit whenever

DCLK changes from low to high. When DR goes low,

the word may then be assembled from the last 8

saved bits.

DATA

may

also

connected

personal

computer’s

serial

communication

port

after

conversion from CMOS to RS-232 voltage levels.

Mode 1 - Buffer Mode

This mode is selected when the CB0 pin is high. In

this mode the received byte is stored on chip. At the

end of a byte DR goes low to indicate that a new byte

has become available. The microcontroller applies

DCLK pulses to read the register contents serially

out of the DATA pin (see Figure 14).

Internal to the MT88E45, the start bit is stripped off,

the data bits and the trailing stop bit are sampled and

stored. Midway through the stop bit, the 8 data bits

and the stop bit are parallel loaded into a 9 bit shift

shifted out to the DATA pin on the supplied DCLK’s

rising edges in the order they were received. The last

bit must be shifted out and DCLK returned to low

before the next DR. DCLK must be low for tDDS before

DR goes low and must remain low for tDDH after DR

has gone low (see Figure 14).

If DCLK begins while DR is low, DR will return to high

upon the ﬁrst DCLK rising edge. If DR interrupts a

microcontroller then this feature allows the interrupt

to be cleared by the ﬁrst read pulse. Otherwise DR is

low for half a nominal bit time (1/2400 sec).

Reading the stop bit allows the software to check for

framing errors. When framing error is not checked

the microcontroller only needs to send 8 DCLK

pulses to shift the data byte out.

Carrier Detect

The carrier detector provides an indication of the

presence of a signal in the FSK frequency band. It

detects the presence of a signal of sufﬁcient

amplitude at the output of the FSK bandpass ﬁlter.

The signal is qualiﬁed by a digital algorithm before

the CD output is set low to indicate carrier detection.

10ms

hysteresis

provided

allow

for

momentary signal dropout once CD has been

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