MT8952BC datasheet(21/22 Pages) MITEL

21 / 22 page

ISO-CMOS

MT8952B

3-81

† Timing is over recommended temperature & power supply voltages (VDD=5V±5%, VSS=0V, TA=–40 to 85°C).

‡ Typical ﬁgures are at 25

°C and are for design aid only: not guaranteed and not subject to production testing.

Figure 23 - Serial Port Inputs and Outputs in External Timing Mode

Note: The frequency of the clock input (CKi) should be at the output bit rate in the External Timing Mode.

Figure 24 - ST-BUS Format

AC Electrical Characteristics† - Serial Port in External Timing Mode - (Figure 23 )

Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics

Sym

Min

Typ‡

Max

Units

Test Conditions

Clock period on CKi pin

tCEX

400

CKi transition time

TxCEN/RxCEN setup time

tCENS

TxCEN/RxCEN hold time

tCENH

CDSTi setup time

tSTiS

CDSTi hold time

tSTiH

CDSTo delay

tSToZL

tSToZH

125

Test load circuit 1 (Fig. 26)

CL=150pF

CDSTo disable time

tSToLZ

tSToHZ

Test load circuit 3 (Fig. 26)

CKi

TxCEN/

RxCEN

CDSTi

CDSTo

VALID DATA

tCEX

tCENS

tCENH

tSTiS

tSTiH

tSToZL

tSToZH

tSToHZ

tSToLZ

HIGH

IMPEDANCE

HIGH IMPEDANCE

Channel

• • • • • • • •

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

125

µsec

Channel

F0i

ST-BUS

Least

Significant

Bit

Most

Significant

Bit

3.9

µsec

(D0 on the Data

Bus)

(D7 on the Data

Bus)

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