MT91L62AS datasheet(5/17 Pages) MITEL

5 / 17 page

Advance Information

MT91L62

7-177

Dout, on the rising edge of BCL during the time slot

deﬁned by the STB input. Dout is tri-stated at all

times when STB is not true. If STB is valid, then quiet

code will be transmitted on Dout during the valid

strobe period. There is no frame delay through the

PCM serial circuit for synchronous operation.

For asynchronous operation Dout and Din are as

deﬁned for synchronous operation except that the

allowed output jitter on Dout is larger. This is due to

the resynchronization circuitry activity and will not

affect operation since the bit cell period at 128 kb/s

and 256 kb/s is relatively large. There is a one frame

delay

through

the

PCM

serial

circuit

for

asynchronous operation. Refer to the speciﬁcations

of Figures 5 & 6 for both synchronous and

asynchronous SSI timing.

PWRST

While the MT91L62 is held in PWRST no device

control or functionality is possible.

Applications

Figure 4 shows an application of the MT91L62 in a

line card.

Figure 4 - Line Card Application

0.1

µF

0.1

µF

VBias

+3V

Dout

Din

Frame Pulse

Clock

MT91L62

100k

CS2

CS1

CS0

TxMUTE

RxMUTE

Timing

Block

Output to Subscriber

Line Interface

Input from Subscriber

Line Interface

0.1

µF

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